Instruction
VFNMSUB213SD
Fused negated multiply-subtract of the low doubles: minus second times first, minus third, into the first; the rest is unchanged.
- Extensions
- Forms
- 4 (2 VEX, 2 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VFNMSUB213SD xmm, xmm, m64
VFNMSUB213SD_XMMdq_XMMq_MEMq | VEX.LIG.66.0F38.W1 AF /r | FMA + AVX |
VFNMSUB213SD xmm, xmm, xmm
VFNMSUB213SD_XMMdq_XMMq_XMMq | VEX.LIG.66.0F38.W1 AF /r | FMA + AVX |
VFNMSUB213SD xmm {k}{z}, xmm, xmm, {er}
VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 | EVEX.LIG.66.0F38.W1 AF /r | AVX10.1 or AVX512F |
VFNMSUB213SD xmm {k}{z}, xmm, m64
VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 | EVEX.LIG.66.0F38.W1 AF /r | AVX10.1 or AVX512F |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VFNMSUB213SD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_fnmsub_round_sd
__m128d _mm_fnmsub_round_sd(__m128d A, __m128d B, __m128d C, const int R) |
|
_mm_fnmsub_sd
__m128d _mm_fnmsub_sd(__m128d __A, __m128d __B, __m128d __C) |
|
_mm_mask_fnmsub_round_sd
__m128d _mm_mask_fnmsub_round_sd(__m128d W, __mmask8 U, __m128d A, __m128d B, const int R) |
|
_mm_mask_fnmsub_sd
__m128d _mm_mask_fnmsub_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) |
|
_mm_maskz_fnmsub_round_sd
__m128d _mm_maskz_fnmsub_round_sd(__mmask8 U, __m128d A, __m128d B, __m128d C, const int R) |
|
_mm_maskz_fnmsub_sd
__m128d _mm_maskz_fnmsub_sd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
FMA | FMA + AVX | Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Piledriver, Zen, Zen+, Zen 2 |
AVX512F_SCALAR | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill |
More AVX10.1 instructions
- VFNMADD213PH
- VFNMADD213PS
- VFNMADD213SD
- VFNMADD213SH
- VFNMADD213SS
- VFNMADD231PD
- VFNMADD231PH
- VFNMADD231PS
- VFNMADD231SD
- VFNMADD231SH
- VFNMADD231SS
- VFNMSUB132PD
- VFNMSUB132PH
- VFNMSUB132PS
- VFNMSUB132SD
- VFNMSUB132SH
- VFNMSUB132SS
- VFNMSUB213PD
- VFNMSUB213PH
- VFNMSUB213PS
- VFNMSUB213SH
- VFNMSUB213SS
- VFNMSUB231PD
- VFNMSUB231PH
- VFNMSUB231PS
- VFNMSUB231SD
- VFNMSUB231SH
- VFNMSUB231SS
- VFPCLASSPD
- VFPCLASSPH
- VFPCLASSPS
- VFPCLASSSD
- VFPCLASSSH
- VFPCLASSSS
- VGATHERDPD
- VGATHERDPS
- VGATHERQPD
- VGATHERQPS
- VGETEXPPD
- VGETEXPPH
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.