VFNMSUB213SH

VFNMSUB213SH computes -(op2 × op1) - op3 on the low halves and rounds once: op1 is a factor and is overwritten, and op3, the operand that may come from memory, is subtracted from the negated product. Bits 127:16 of the destination stay as they were and the bits above 127 are cleared. It is the scalar form of VFNMSUB213PH; VFNMSUB132SH and VFNMSUB231SH are the other operand orders, and VFNMSUB213SS the single-precision form. The encoding is AFh with the 66 prefix in EVEX map 6; it takes {er} between registers and reads two bytes from memory.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 compiles the expression -(x * y) - z on _Float16 values to VFNMSUB213SH, and __builtin_fmaf16(-x, y, -z), _mm_fnmsub_sh and the masked _mm_mask_fnmsub_sh and _mm_maskz_fnmsub_sh too; GCC 14 picks VFNMSUB132SH for all of these. Both use VFNMSUB213SH when the subtracted value comes from memory, as in -(x * y) - a[5]. A constant is added negated instead: -(x * y) - 1 becomes VFNMADD213SH adding -1.

In a loop r[i] = -(p[i] * q[i]) - r[i] through pointer parameters, Clang loads both factors and reads r[i] in place with VFNMSUB213SH for short or overlapping arrays, and otherwise runs VFNMSUB213PH on ymm registers after a run-time check that the arrays do not overlap. GCC adds no such check at -O2 and keeps the loop scalar with VFNMSUB132SH and q[i] from memory; with restrict on the parameters a constant 1,024 elements run VFNMSUB132PH on zmm registers, while a count known only at run time stays scalar either way. At -O3 GCC checks for overlap too and vectorizes.

Intel’s optimization manual counts the fused multiply-add among the FP16 operations that are correctly rounded, to 0.5 ULP when rounding to nearest (Section 18.5.3).

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMSUB213SH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm1.f16[0]
    b = xmm2.f16[0]
    c = src3.f16[0]
    xmm1.f16[0] = fnmsub(b, a, c)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
# xmm1.w[1] to [7] keep their values
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMSUB213SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SH
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS

All 686 AVX10.1 instructions