x86-64.net

Instruction

VFNMSUB231PD

Fused negated multiply-subtract of packed doubles: minus second operand times third, minus first, into the first.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VFNMSUB231PD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VFNMSUB231PD xmm, xmm, m128 VFNMSUB231PD_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.W1 BE /rFMA + AVX
VFNMSUB231PD xmm, xmm, xmm VFNMSUB231PD_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.W1 BE /rFMA + AVX
VFNMSUB231PD ymm, ymm, m256 VFNMSUB231PD_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.W1 BE /rFMA + AVX
VFNMSUB231PD ymm, ymm, ymm VFNMSUB231PD_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.W1 BE /rFMA + AVX
VFNMSUB231PD zmm {k}{z}, zmm, zmm, {er} VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512EVEX.512.66.0F38.W1 BE /rAVX10.1 or AVX512F
VFNMSUB231PD zmm {k}{z}, zmm, m512/m64bcst VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512EVEX.512.66.0F38.W1 BE /rAVX10.1 or AVX512F
VFNMSUB231PD xmm {k}{z}, xmm, xmm VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512EVEX.128.66.0F38.W1 BE /rAVX10.1 or AVX512F + AVX512VL
VFNMSUB231PD xmm {k}{z}, xmm, m128/m64bcst VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512EVEX.128.66.0F38.W1 BE /rAVX10.1 or AVX512F + AVX512VL
VFNMSUB231PD ymm {k}{z}, ymm, ymm VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512EVEX.256.66.0F38.W1 BE /rAVX10.1 or AVX512F + AVX512VL
VFNMSUB231PD ymm {k}{z}, ymm, m256/m64bcst VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512EVEX.256.66.0F38.W1 BE /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMSUB231PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_fnmsub_pd __m128d _mm_fnmsub_pd(__m128d __A, __m128d __B, __m128d __C)

VFNMSUB231PD xmm, xmm, xmm VEX.128 -mfmawhen __C is already in the destination register

_mm_mask3_fnmsub_pd __m128d _mm_mask3_fnmsub_pd(__m128d __A, __m128d __B, __m128d __C, __mmask8 __U)

VFNMSUB231PD xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_fnmsub_pd __m128d _mm_maskz_fnmsub_pd(__mmask8 __U, __m128d __A, __m128d __B, __m128d __C)

VFNMSUB231PD xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vlwhen __C is already in the destination register

_mm256_fnmsub_pd __m256d _mm256_fnmsub_pd(__m256d __A, __m256d __B, __m256d __C)

VFNMSUB231PD ymm, ymm, ymm VEX.256 -mfmawhen __C is already in the destination register

_mm256_mask3_fnmsub_pd __m256d _mm256_mask3_fnmsub_pd(__m256d __A, __m256d __B, __m256d __C, __mmask8 __U)

VFNMSUB231PD ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_fnmsub_pd __m256d _mm256_maskz_fnmsub_pd(__mmask8 __U, __m256d __A, __m256d __B, __m256d __C)

VFNMSUB231PD ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vlwhen __C is already in the destination register

_mm512_fnmsub_pd __m512d _mm512_fnmsub_pd(__m512d __A, __m512d __B, __m512d __C)

VFNMSUB231PD zmm, zmm, zmm EVEX.512 -mavx512fwhen __C is already in the destination register

_mm512_fnmsub_round_pd __m512d _mm512_fnmsub_round_pd(__m512d A, __m512d B, __m512d C, const int R)

VFNMSUB231PD zmm, zmm, zmm, {er} EVEX.512 -mavx512fwhen C is already in the destination register

_mm512_mask3_fnmsub_pd __m512d _mm512_mask3_fnmsub_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U)

VFNMSUB231PD zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_mask3_fnmsub_round_pd __m512d _mm512_mask3_fnmsub_round_pd(__m512d A, __m512d B, __m512d C, __mmask8 U, const int R)

VFNMSUB231PD zmm {k}, zmm, zmm, {er} EVEX.512 -mavx512f

_mm512_maskz_fnmsub_pd __m512d _mm512_maskz_fnmsub_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512d __C)

VFNMSUB231PD zmm {k}{z}, zmm, zmm EVEX.512 -mavx512fwhen __C is already in the destination register

_mm512_maskz_fnmsub_round_pd __m512d _mm512_maskz_fnmsub_round_pd(__mmask8 U, __m512d A, __m512d B, __m512d C, const int R)

VFNMSUB231PD zmm {k}{z}, zmm, zmm, {er} EVEX.512 -mavx512fwhen C is already in the destination register

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
FMA

FMA + AVX
CPUID.01H:ECX[12] FMA
CPUID.01H:ECX[28] AVX

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Piledriver, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.