VFNMSUB231PH

VFNMSUB231PH computes -(op2 × op3) - op1 for each half-precision element and rounds once: both the product and the destination’s old value are negated, with one factor from memory or broadcast from a single half. VFNMSUB231PS explains the form for singles, with cases recorded on Zen 5 that show how it differs from a negated VFMADD; VFNMSUB132PH covers the FP16 forms and VFMADD132PH what a merge mask keeps in each order: here the unselected elements keep the subtracted value. The opcode is BEh with the 66 prefix in EVEX map 6.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile _mm512_mask3_fnmsub_ph(a, b, c, k), which must keep c where the mask is clear, to VFNMSUB231PH with c as destination. A loop that feeds the result back as the third operand, acc = _mm512_fnmsub_ph(x, y, acc), uses it in GCC on every pass, with y read from memory; Clang unrolls the loop and mixes it with VFNMSUB132PH.

The singles’ page shows Clang compiling s -= x[i] * y[i] over floats with -ffast-math to VMULPS and VFNMSUB231PS. Over _Float16 arrays it does not reach VFNMSUB231PH: it pairs a VMULPH with a VFMADD231PH and subtracts the sum from one of four ymm accumulators with VSUBPH, while GCC accumulates with VFNMADD231PH in a zmm register. Without -ffast-math, Clang keeps a chain of scalar VFNMADD forms and GCC subtracts VMULPH products one at a time with VSUBSH.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMSUB231PH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm1.f16[i]
        b = zmm2.f16[i]
        c = src3.f16[i]
        zmm1.f16[i] = fnmsub(b, c, a)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMSUB231PH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS

All 686 AVX10.1 instructions