VFNMSUB231PS

VFNMSUB231PS computes -(op2 × op3) - op1 for each single, rounded once: both the product and the destination’s old value are negated. VFNMADD231PS sets the four sign variants of the FMA family side by side and shows the signs of their NaNs, and VFMADD231PS explains the three digits and the masking, broadcast and {er} rounding of the EVEX forms.

Not quite a negated VFMADD#

-(x × y) - z equals -(x × y + z), but the instruction negates its inputs and rounds afterwards, and two cases recorded on Zen 5 show the difference:

• In vfnmsub231ps ymm1, ymm2, ymmword ptr [mem] under MXCSR 7F80H (toward zero), -(1 × 1) - (-1) returned +0, the sign of an exact zero sum of opposite signs; VFMADD’s 1 × 1 + (-1) is +0 too, and its negation -0.
• In vfnmsub231ps xmm7, xmm11, xmm7 under 3FC0H (round down, DAZ), -(10^-30 × 10^-30) - 10^-30 gave 8DA24261H, the single below -10^-30: rounding down moves a negative result away from zero, where a negated VFMADD rounded down would have returned -10^-30 itself. For 10^30 the same instruction overflowed to minus infinity and set OE and PE; under {ru-sae}, in vfnmsub231ps zmm17{k7}, zmm30, zmm2, -(10^30 × 10^30) + 10^30 stopped at the most negative finite single.

In our builds#

At -O2 with -ffast-math, Clang 23 compiles s -= x[i] * y[i] over floats by multiplying one pair with VMULPS, folding the next in with VFNMSUB231PS, -(x × y) - p, and adding that to one of four ymm sums, for both -march=x86-64-v3 and -v4. With the values in memory, a[i] = -(b[i] * c[i]) - d[i] becomes VFNMSUB213PS in Clang and VFNMSUB132PS in GCC 14, with or without -ffast-math.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 4 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm1.f32[i]
        b = zmm2.f32[i]
        c = src3.f32[i]
        zmm1.f32[i] = fnmsub(b, c, a)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMSUB231PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More FMA instructions

• VFMSUB132PS
• VFMSUB132SD
• VFMSUB132SS
• VFMSUB213PD
• VFMSUB213PS
• VFMSUB213SD
• VFMSUB213SS
• VFMSUB231PD
• VFMSUB231PS
• VFMSUB231SD
• VFMSUB231SS
• VFMSUBADD132PD
• VFMSUBADD132PS
• VFMSUBADD213PD
• VFMSUBADD213PS
• VFMSUBADD231PD
• VFMSUBADD231PS
• VFNMADD132PD
• VFNMADD132PS
• VFNMADD132SD
• VFNMADD132SS
• VFNMADD213PD
• VFNMADD213PS
• VFNMADD213SD
• VFNMADD213SS
• VFNMADD231PD
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231SD
• VFNMSUB231SS

All 60 FMA instructions

More AVX10.1 instructions

• VFNMADD231PD
• VFNMADD231PH
• VFNMADD231PS
• VFNMADD231SD
• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD

All 686 AVX10.1 instructions