VFNMSUB231SH instruction (AVX10.1)

VFNMSUB231SH computes -(op2 × op3) - op1 on the low halves and rounds once: both the product and the destination’s old value are negated. Bits 127:16 of the destination stay as they were and the bits above 127 are cleared. It is the scalar form of VFNMSUB231PH; VFNMSUB132SH and VFNMSUB213SH are the other operand orders, and VFNMSUB231SS the single-precision form. The encoding is BFh with the 66 prefix in EVEX map 6; it takes {er} and reads two bytes when op3 is in memory.

In our builds

The 231 order fits when the subtracted value is the one that arrives first. At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile a function -(x * y) - s whose first _Float16 argument is s, already in XMM0, to a single VFNMSUB231SH with XMM0 as destination; with s last, they pick the 132 or 213 order and the result lands in XMM0 anyway. The masked _mm_mask3_fnmsub_sh(a, b, c, k), which keeps c when bit 0 of the mask is clear, is VFNMSUB231SH in both too, with c as destination and a move to the return register after.

The same holds for the other scalar FMAs: x * y - s with s first becomes VFMSUB231SH, and a - q * b with a first VFNMADD231SH, so the operand order the compilers choose often follows the register each argument arrives in.

Intel’s optimization manual counts the fused multiply-add among the FP16 operations that are correctly rounded, to 0.5 ULP when rounding to nearest (Section 18.5.3).

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFNMSUB231SH.

Forms

Every encoding of VFNMSUB231SH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VFNMSUB231SH xmm {k}{z}, xmm, xmm, {er}` VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512	`EVEX.LIG.66.MAP6.W0 BF /r`	AVX10.1 or AVX512_FP16
`VFNMSUB231SH xmm {k}{z}, xmm, m16` VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512	`EVEX.LIG.66.MAP6.W0 BF /r`	AVX10.1 or AVX512_FP16

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm {k}{z}, xmm, xmm, {er}`no mask, with {er}	`xmm {k}{z}, xmm, xmm, {er}`with a mask, zeroing	`xmm {k}{z}, xmm, m16`
Sapphire Rapids	5 / 0.5p01	6 / 0.5p01	12 / 0.5p01

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low half is computed; the other halves come from xmm1.

The write mask k1 applies to the low half: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result half 0 is computed from half 0 of xmm1, xmm2 and xmm3; halves 7 to 1 are those of xmm1. Result halves 7 to 0: a7, a6, a5, a4, a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm1.f16[0]
    b = xmm2.f16[0]
    c = src3.f16[0]
    xmm1.f16[0] = fnmsub(b, c, a)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
# xmm1.w[1] to [7] keep their values
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Not run on a processor: none of these processors has AVX512-FP16. The tests check its arithmetic against MPFR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VFNMSUB231SH xmm {k}{z}, xmm, xmm/m16, {er}`
`xmm`	explicit	read, write (masked)
`{k}`	explicit	read (write mask)
`xmm`	explicit	read
`xmm/m16`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms: write masking; follows MXCSR
Memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFNMSUB231SH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mask3_fnmsub_round_sh` `__m128h _mm_mask3_fnmsub_round_sh(__m128h W, __m128h X, __m128h Y, __mmask8 U, const int R)`	`VFNMSUB231SH xmm {k}, xmm, xmm, {er}` EVEX.LIG -mavx512fp16
`_mm_mask3_fnmsub_sh` `__m128h _mm_mask3_fnmsub_sh(__m128h __W, __m128h __X, __m128h __Y, __mmask8 __U)`	`VFNMSUB231SH xmm {k}, xmm, xmm` EVEX.LIG -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512_FP16_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

AVX512_FP16_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

In our builds#