x86-64.net

Instruction

VFPCLASSBF16

Tests packed bfloat16 values for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VFPCLASSBF16 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VFPCLASSBF16 k {k}, xmm, imm8 VFPCLASSBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512EVEX.128.F2.0F3A.W0 66 /r ibAVX10.2
VFPCLASSBF16 k {k}, m128/m16bcst, imm8 VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128EVEX.LLZ.F2.0F3A.W0 66 /r ibAVX10.2
VFPCLASSBF16 k {k}, ymm, imm8 VFPCLASSBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512EVEX.256.F2.0F3A.W0 66 /r ibAVX10.2
VFPCLASSBF16 k {k}, m256/m16bcst, imm8 VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256EVEX.LLZ.F2.0F3A.W0 66 /r ibAVX10.2
VFPCLASSBF16 k {k}, zmm, imm8 VFPCLASSBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512EVEX.512.F2.0F3A.W0 66 /r ibAVX10.2
VFPCLASSBF16 k {k}, m512/m16bcst, imm8 VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512EVEX.LLZ.F2.0F3A.W0 66 /r ibAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFPCLASSBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_fpclass_pbh_mask __mmask8 _mm_fpclass_pbh_mask(__m128bh __A, const int imm)

VFPCLASSBF16 k, xmm, imm8 EVEX.128 -mavx10.2

_mm_mask_fpclass_pbh_mask __mmask8 _mm_mask_fpclass_pbh_mask(__mmask8 __U, __m128bh __A, const int imm)

VFPCLASSBF16 k, xmm, imm8 EVEX.128 -mavx10.2

_mm256_fpclass_pbh_mask __mmask16 _mm256_fpclass_pbh_mask(__m256bh __A, const int imm)

VFPCLASSBF16 k, ymm, imm8 EVEX.256 -mavx10.2

_mm256_mask_fpclass_pbh_mask __mmask16 _mm256_mask_fpclass_pbh_mask(__mmask16 __U, __m256bh __A, const int imm)

VFPCLASSBF16 k, ymm, imm8 EVEX.256 -mavx10.2

_mm512_fpclass_pbh_mask __mmask32 _mm512_fpclass_pbh_mask(__m512bh __A, const int imm)

VFPCLASSBF16 k, zmm, imm8 EVEX.512 -mavx10.2

_mm512_mask_fpclass_pbh_mask __mmask32 _mm512_mask_fpclass_pbh_mask(__mmask32 __U, __m512bh __A, const int imm)

VFPCLASSBF16 k, zmm, imm8 EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX10_2_BF16_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX10_2_BF16_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX10_2_BF16_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.