VFPCLASSBF16

VFPCLASSBF16 tests each bfloat16 value of its source for the classes its immediate selects and sets a mask bit where the element falls into any of them, up to 32 bits for a zmm register. The eight classes and their bits are those of VFPCLASSPS: from bit 0, quiet NaN, +0, -0, +infinity, -infinity, denormal, negative finite and signaling NaN. It belongs to AVX10.2; the opcode is 66h in map 0F3A with the F2 prefix and W0, where VFPCLASSPH has no prefix and VFPCLASSPS 66. The source may be broadcast from 16 bits of memory, a write mask clears the result bits it leaves out, and EVEX.vvvv must be 1111b.

Denormals are zeros#

Like the rest of AVX10.2’s bfloat16 instructions, VFPCLASSBF16 reads denormals as zeros and ignores MXCSR, as VADDBF16’s page explains. So a denormal always matches +0 or -0, bit 5 never matches anything, and a negative denormal does not match bit 6, the reverse of VFPCLASSPH, which always sees the denormal.

The specification’s routine (revision 7.0) shows this in a way that needs reading with care. It sets its “mantissa all zeros” flag to 1 when the exponent is zero, which is the DAZ step, and when the fraction is zero, and its comment says the denormal class is always 0 for bfloat16. But no branch sets the flag to 0: for a NaN, whose fraction is not zero, it is never assigned, so as written the routine does not tell a NaN from an infinity. The description and the class names show that a test of the fraction is meant.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 compiles _mm512_fpclass_pbh_mask(x, 0x81), both kinds of NaN, to vfpclassbf16 k0, zmm0, 129 and a KMOVD. Loops over __bf16 arrays do not use it: isnan is a VCMPBF16 for unordered of each vector with itself, and isinf clears the sign bits with VPANDQ and compares the words with 7F80h by VPCMPEQW. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    a = src2.bf16[i]
    k1[i] = k2[i] and fpclass(imm8, a)
# imm8 bits: 0 QNaN, 1 +0, 2 -0, 3 +inf, 4 -inf, 5 denormal, 6 negative, 7 SNaN
# m16bcst: src2.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; denormal inputs read as zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFPCLASSBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTTPS2UDQS
• VCVTTPS2UQQS
• VCVTTSD2SIS
• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD

All 96 AVX10.2 instructions