VFPCLASSPD

VFPCLASSPD is VFPCLASSPS for doubles: the same eight classes, quiet NaN in immediate bit 0 up to signaling NaN in bit 7, and one mask bit per element, so at most 8, with the bits above cleared. That page explains how the classes overlap and how DAZ turns denormals into zeros; VFPCLASSSD tests only the low double.

Recorded on Zen 5#

The 6 cases agree with the classifier in Intel’s manual.

• Denormals. With immediate 66h (+0, -0, denormal, negative finite) and DAZ clear, 0000000000000001h, 000FFFFFFFFFFFFFh and 8008000000000000h set their bits and 2^-1022, the smallest normal, did not. FTZ was set in that case, and the manual’s classifier ignores it: it acts on floating-point results, and there are none.
• Negative finite (40h) excludes the zeros and NaNs: with only that bit, -0, a quiet NaN and the negative signaling NaN FFF0000000000001h set no bit, while with 66h -1.0 set its bit.

Divisors that need no refinement#

Intel’s optimization manual divides doubles to 52 bits with VRCP14PD and FMAs (Section 17.25.4, Example 17-41). For a divisor of +0, -0, +infinity or -infinity the estimate is already exact, so vfpclasspd k2, zmm1, 0x1e marks those lanes and VBLENDMPD’s page follows the rest of the sequence.

In compiled code#

GCC 14 and Clang 23 at -O2, for -march=x86-64-v4 or -march=znver5, emit it only for _mm512_fpclass_pd_mask and its kin; isinf, isnan, isfinite and isnormal over double arrays compile to VCMPPD or integer compares, as for floats. Clang annotates the intrinsic’s immediate in its assembly: 1Eh is isPositiveZero | isNegativeZero | isPositiveInfinity | isNegativeInfinity.

AMD’s Zen 5 latency spreadsheet gives VFPCLASSPD the same figures as VFPCLASSPS: 3, 4 and 6 cycles at 128, 256 and 512 bits, two per cycle on pipes FP1 and FP2.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    a = src2.f64[i]
    k1[i] = k2[i] and fpclass(imm8, a)
# imm8 bits: 0 QNaN, 1 +0, 2 -0, 3 +inf, 4 -inf, 5 denormal, 6 negative, 7 SNaN
# m64bcst: src2.f64[i] is the m64 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFPCLASSPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMADD231SH
• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH

All 686 AVX10.1 instructions