VFPCLASSPH

VFPCLASSPH tests each half of its source for the classes its immediate selects and sets a mask bit where the element falls into any of them, up to 32 bits for a zmm register. The eight classes and their bits are those of VFPCLASSPS: from bit 0, quiet NaN, +0, -0, +infinity, -infinity, denormal, negative finite and signaling NaN. It only reads bits, so it raises no SIMD exception, and a write mask clears the result bits of the elements it leaves out. VADDPH covers the format and the CPUID bits; the opcode is 66h in the 0F3A map with no prefix, where VFPCLASSPS has the 66 prefix, as VGETMANTPH explains.

No DAZ#

Intel’s classifier for halves has no DAZ step, where that of singles reads a denormal as a zero when MXCSR.DAZ is set: FP16 instructions ignore DAZ (Intel’s optimization manual, Section 18.5.4). So a denormal half always matches bit 5, and a negative one bit 6 as well, never +0 or -0. In FP16 code that matters more than for singles: the smallest normal half is only 2^-14, and the manual expects denormal inputs to be common in vectorized FP16 math functions, which use the classification to send special inputs to a separate path or to fix up their results (Section 18.7).

In our builds#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 -mavx512fp16 compile _mm512_fpclass_ph_mask(x, 0x81), both kinds of NaN, to VFPCLASSPH into K0 and a KMOVD. Loops of the classification macros over _Float16 arrays do not use it: isnan is a VCMPPH with the unordered predicate of each vector with itself, and isinf and isfinite clear the sign bits with VPANDD or VPAND and compare what is left: GCC with VCMPPH against the largest finite half, Clang against infinity, as words with VPCMPEQW for isinf. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFPCLASSPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    a = src2.f16[i]
    k1[i] = k2[i] and fpclass(imm8, a)
# imm8 bits: 0 QNaN, 1 +0, 2 -0, 3 +inf, 4 -inf, 5 denormal, 6 negative, 7 SNaN
# m16bcst: src2.f16[i] is the m16 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFPCLASSPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMADD231SS
• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS

All 686 AVX10.1 instructions