VFPCLASSPS

VFPCLASSPS sorts each single of its source into classes and sets a mask bit where the element falls into any class the immediate selects. From bit 0 the immediate picks quiet NaN, +0, -0, +infinity, -infinity, denormal, negative finite and signaling NaN. A write mask clears the bits of the elements it leaves out, as for a compare into a mask register, and the bits above the last element are cleared. VFPCLASSPD is the double form and VFPCLASSSS the scalar one; all need AVX512DQ. It only looks at bits, so it raises no SIMD exception and sets no flag.

Recorded on Zen 5#

All 44 cases agree, bit for bit, with the classifier in Intel’s manual.

• Classes overlap. Without DAZ, the negative denormal 80400000h set its bit with immediate 66h both as a denormal and as negative finite; “negative finite” takes in neither -0 nor -infinity.
• DAZ turns denormals into zeros. Under DAZ, 00000001h and 007FFFFFh matched +0 (immediate 02h) and 80400000h matched -0 (04h), and none of them matched denormal (20h) or negative finite (40h).
• Signaling NaNs stay silent. With MXCSR 0, every exception unmasked, immediate 66h ran over four signaling NaNs without a fault, and MXCSR came out unchanged in all 44 cases. Immediate 81h, either NaN, caught 7F812345h; immediate 0 sets no bit.

Special lanes#

Intel’s optimization manual uses it to keep special inputs out of a refinement (Section 17.15.6). In its square root from VRSQRT14PS (Example 17-40), immediate 0Eh marks +0, -0 and +infinity, each its own square root, and KNOTW inverts that mask for the FMAs, so those lanes keep the input.

In compiled code#

GCC 14 and Clang 23 at -O2, for -march=x86-64-v4 or -march=znver5, emit it only for _mm512_fpclass_ps_mask and its kin. Loops of isinf, isnan, isfinite or isnormal over float arrays become VCMPPS, mostly on the absolute value against infinity, or in Clang integer compares of the bits for isinf and isnormal.

AMD’s Zen 5 latency spreadsheet gives VFPCLASSPS 3 cycles at 128 bits, 4 at 256 and 6 at 512, two per cycle on pipes FP1 and FP2, with a second macro-op for a memory source.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    a = src2.f32[i]
    k1[i] = k2[i] and fpclass(imm8, a)
# imm8 bits: 0 QNaN, 1 +0, 2 -0, 3 +inf, 4 -inf, 5 denormal, 6 negative, 7 SNaN
# m32bcst: src2.f32[i] is the m32 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFPCLASSPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMSUB132PD
• VFNMSUB132PH
• VFNMSUB132PS
• VFNMSUB132SD
• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB

All 686 AVX10.1 instructions