VFPCLASSSH instruction (AVX10.1)

VFPCLASSSH tests the low half of its source for the classes that its immediate selects and writes the answer to bit 0 of a mask register, clearing all the other bits. The eight classes and their immediate bits are those of VFPCLASSPH, whose page explains that FP16 has no DAZ case, so a denormal half always counts as a denormal and never as a zero. With a write mask, a clear bit 0 in it gives 0 whatever the class. It reads bits only and raises no SIMD exception. The encoding is 67h in the 0F3A map with no prefix, where VFPCLASSSS has 66; the source is an xmm register or two bytes of memory, and EVEX.vvvv must be 1111b. VADDPH covers the format and the CPUID bits.

The classification macros do without it

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 emit VFPCLASSSH only for the intrinsic: _mm_fpclass_sh_mask(x, 0x81), both kinds of NaN, becomes vfpclasssh k0, xmm0, 129 and a KMOV to a general-purpose register. C’s macros on a _Float16 value use other instructions. isnan(x) compares x with itself by VUCOMISH and reads the parity flag. For isinf and isfinite, GCC clears the sign with VANDPS and compares with VUCOMISH against the largest finite half, while Clang moves the bits to a general-purpose register with VMOVW and tests them as an integer, isinf by comparing them, sign cleared, with 7C00h, the bits of infinity; issignaling and signbit are integer tests of those bits in both. With -ffast-math both fold isnan and isinf to 0 and isfinite to 1.

Intel’s optimization manual names VFPCLASS among the FP16 instructions for math libraries, which use it to send special inputs to a separate path or to build a mask for fixing up results (Section 18.7).

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VFPCLASSSH.

Forms

Every encoding of VFPCLASSSH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VFPCLASSSH k {k}, xmm, imm8` VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512	`EVEX.LIG.NP.0F3A.W0 67 /r ib`	AVX10.1 or AVX512_FP16
`VFPCLASSSH k {k}, m16, imm8` VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512	`EVEX.LIG.NP.0F3A.W0 67 /r ib`	AVX10.1 or AVX512_FP16

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k {k}, xmm, imm8`	`k {k}, m16, imm8`no mask	`k {k}, m16, imm8`with a mask
Sapphire Rapids	3 / 1p5	9 / 1p5	3 / 1p5

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Only the low half counts: the result goes to bit 0 of k1, and its other bits are cleared.

Where bit 0 of the write mask k2 is 0, the result bit is 0.

The result comes from half 0 of xmm2. Result bits 7 to 0: 0, 0, 0, 0, 0, 0, 0, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1[0] = k2[0] and fpclass(imm8, src2.f16[0])
# imm8 bits: 0 QNaN, 1 +0, 2 -0, 3 +inf, 4 -inf, 5 denormal, 6 negative, 7 SNaN
# the other bits of k1 are cleared

Not run on a processor: none of these processors has AVX512-FP16.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VFPCLASSSH k {k}, xmm/m16, imm8`
`k`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`xmm/m16`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms: write masking
Memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFPCLASSSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_fpclass_sh_mask` `__mmask8 _mm_fpclass_sh_mask(__m128h A, const int imm)`	`VFPCLASSSH k, xmm, imm8` EVEX.LIG -mavx512fp16
`_mm_mask_fpclass_sh_mask` `__mmask8 _mm_mask_fpclass_sh_mask(__mmask8 U, __m128h A, const int imm)`	`VFPCLASSSH k {k}, xmm, imm8` EVEX.LIG -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512_FP16_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

AVX512_FP16_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

The classification macros do without it#