VFPCLASSSS instruction (AVX10.1)

VFPCLASSSS tests the low single of an XMM register, or a single in memory, for the classes its immediate selects, and writes the answer to bit 0 of a mask register, clearing every bit above it. The classes, from quiet NaN in immediate bit 0 to signaling NaN in bit 7, are those of VFPCLASSPS, whose page explains how they overlap and how DAZ turns denormals into zeros. A positive normal number falls into none of them. With a write mask, a clear bit 0 in it gives 0 whatever the class. It came with AVX512DQ, reads bits only and raises no SIMD exception, not even for a signaling NaN. VFPCLASSSD is the double form and VFPCLASSSH the half-precision one.

Recorded on Zen 5

Infinities. vfpclassss k3{k5}, xmm24, 0x18, +infinity or -infinity, cleared K3 for -1.0.
No class. Immediate FFh cleared K1 for 3F800001h, the single just above 1.0, with bit 0 of the write mask K2 set.

In compiled code

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 emit VFPCLASSSS only for the intrinsic: _mm_fpclass_ss_mask(x, 0x18) becomes vfpclassss k0, xmm0, 24 and a KMOVB to a general-purpose register. For isnan(x) || x == 0.0f, GCC compares with VUCOMISS twice, while Clang compares once with zero and keeps ZF, which an unordered compare also sets.

AMD’s Zen 5 latency spreadsheet gives the same figures as for VFPCLASSSD: one macro-op on pipe FP1 or FP2 and 3 cycles, with a second macro-op for a memory source.

Forms

Every encoding of VFPCLASSSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VFPCLASSSS k {k}, xmm, imm8` VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512	`EVEX.LIG.66.0F3A.W0 67 /r ib`	AVX10.1 or AVX512DQ
`VFPCLASSSS k {k}, m32, imm8` VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512	`EVEX.LIG.66.0F3A.W0 67 /r ib`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k {k}, xmm, imm8`	`k {k}, m32, imm8`no mask	`k {k}, m32, imm8`with a mask
Skylake-SP, Ice Lake	4 / 1p5	9 / 1p5	9 / 1p5
Sapphire Rapids	3 / 1p5	9 / 1p5	3 / 1p5
Zen 4	2 / 1FP0 FP1	9 / 1FP0 FP1	9 / 1FP0 FP1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Only the low single counts: the result goes to bit 0 of k1, and its other bits are cleared.

Where bit 0 of the write mask k2 is 0, the result bit is 0.

The result comes from single 0 of xmm2. Result bits 3 to 0: 0, 0, 0, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

k1[0] = k2[0] and fpclass(imm8, src2.f32[0])
# imm8 bits: 0 QNaN, 1 +0, 2 -0, 3 +inf, 4 -inf, 5 denormal, 6 negative, 7 SNaN
# the other bits of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VFPCLASSSS k {k}, xmm/m32, imm8`
`k`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`xmm/m32`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms: write masking; follows MXCSR
Memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VFPCLASSSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_fpclass_ss_mask` `__mmask8 _mm_fpclass_ss_mask(__m128 A, const int imm)`	`VFPCLASSSS k, xmm, imm8` EVEX.LIG -mavx512dq
`_mm_mask_fpclass_ss_mask` `__mmask8 _mm_mask_fpclass_ss_mask(__mmask8 U, __m128 A, const int imm)`	`VFPCLASSSS k {k}, xmm, imm8` EVEX.LIG -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512DQ_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

AVX512DQ_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Recorded on Zen 5#

In compiled code#