VGATHERDPD

VGATHERDPD loads doubles from scattered addresses, each a base plus a signed 32-bit index times a scale. VGATHERDPS explains the rest, which is the same here: the mask that selects the elements and is cleared as they load, the register rules that raise #UD, the faults it can resume after, and why compiled code rebuilds the mask before each gather. VPGATHERQQ compares the widths of index and data.

Half as many indices as bytes#

A 32-bit index fetching a 64-bit element means the index register is half the width of the destination: four doubles in a ymm register take their indices from an xmm register, and eight in a zmm register from a ymm one. The 128-bit form fetches two doubles and reads only the low two indices of its xmm index register. The cases recorded on Zen 5 show it:

• vgatherdpd xmm1, qword ptr [base + xmm3*8], xmm2 used index 0 for element 1, the only one whose mask had its sign bit set, and ignored the upper two doublewords of xmm3; element 0 kept its old value, and all of xmm2 was cleared.
• vgatherdpd ymm7, qword ptr [base + xmm14*8], ymm5 loaded the elements at indices 3, -5 and -4, below and above the base, and kept element 2, whose mask was clear.
• vgatherdpd zmm17{k7}, qword ptr [base + ymm30*1], with a scale of 1, read a double 36 bytes below the base, an address that is not a multiple of 8, into elements 0 and 7, whose indices were equal, and another 32 bytes above it into elements 5 and 6; k7 ended zero.

In compiled code#

For d[i] = t[idx[i]] with int indices and double data, Clang 23 at -O2 gathers four doubles per instruction with xmm indices for -march=skylake (VEX), x86-64-v4 and icelake-server (EVEX), and eight with ymm indices for znver4 and znver5; for x86-64-v3 it keeps the loop scalar, and GCC 14 does so for every one of these targets. For _mm256_i32gather_pd, GCC makes the all-ones mask with VCMPPD of a zeroed register with itself, and Clang with VPCMPEQD.

In the optimization guide

What the optimization guide says about VGATHERDPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Where the layout of the data is known, vector loads and shuffles usually beat a gather.
• Gathers and scatters: Gathers beat scalar loads on Skylake, while AMD lists them as microcode on Zen 3, Zen 4 and Zen 5.

Crestmont and Gracemont

• Vectors and AVX2: Gathers are microcoded on these cores and take about 50 cycles.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: A gather is a load micro-op for each element plus a few more: LLVM’s models give an eight-element VPGATHERDD 12 micro-ops and a latency of 30 cycles, and the 16-element one of Sapphire Rapids 19 micro-ops.

Haswell and Broadwell

• Gathers: Haswell is the first core with gathers, and each one runs as many micro-ops; Broadwell runs them much faster.

Skylake to Cooper Lake

• Vectors on all parts: Gathers are faster than on Broadwell and beat a sequence of scalar loads unless they fetch only two elements or the data comes from memory rather than the caches.

Zen 2

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, in AMD’s spreadsheet and LLVM’s model, so vector loads and shuffles beat them when the indices are known in advance.

Zen 3

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, and a register loaded in pieces is slower than one full-width load, so vector loads and shuffles beat both when the indices are known in advance.

Zen 4

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance, and a register loaded in pieces is slower than one full-width load.

Zen 5

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = mem.index.number
if x in (ymm1.number, ymm3.number):
    fault(UD)
if ymm1.number == ymm3.number:
    fault(UD)
for i in range(VL // 64):
    if ymm3.sq[i] < 0:
        a = mem.index.sd[i] * mem.scale
        ymm1.q[i] = load(mem.base + a, 64)
ymm3.write(0)
# ymm1 is zeroed from bit VL up

if mem.index.number == zmm1.number:
    fault(UD)
for i in range(VL // 64):
    if k1[i]:
        a = mem.index.sd[i] * mem.scale
        zmm1.q[i] = load(mem.base + a, 64)
k1.write(0)  # all of it
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-12

EVEX forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

gather

EVEX forms

write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGATHERDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VBROADCASTI128
• VBROADCASTSD
• VBROADCASTSS
• VEXTRACTI128
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VINSERTI128
• VMOVNTDQA
• VMPSADBW
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VFNMSUB132SH
• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8

All 686 AVX10.1 instructions