VGATHERDPS

VGATHERDPS loads singles from scattered addresses: element i comes from a base address plus element i of an index vector, a signed 32-bit integer, times a scale of 1, 2, 4 or 8. This is d[i] = t[idx[i]] in one instruction. A mask chooses which elements are loaded; the others keep the destination’s old values, and their addresses are never accessed, so they cannot fault.

The two encodings take the mask differently:

• AVX2 (VEX): a third vector register, whose elements select by their sign bits. The destination, the index and the mask must be three different registers, or the instruction raises #UD.
• AVX-512 (EVEX): a mask register, which cannot be K0 since a gather must have a mask, and only merging, no {z}. The destination must differ from the index register.

The mask is consumed#

The instruction clears each mask element as its load completes, and ends with the whole mask zero: the cases recorded on Zen 5 show all 64 bits of the mask register cleared, even for an XMM gather of four elements. If a load faults partway, the elements already loaded stay written with their mask bits cleared, so that the instruction resumes where it stopped. Compiled code therefore rebuilds the mask before every gather: for _mm256_i32gather_ps, GCC 14 and Clang 23 at -O2 make an all-ones vector each time, and KXNORW makes an all-ones mask register for the EVEX form. Clang also zeroes the destination first, so that the gather does not wait for whatever wrote it last, as Intel’s optimization guide recommends (Section 15.16.4); GCC does not, and copies the index to another register to keep the three apart.

When to use it#

Neither compiler vectorized a loop like d[i] = t[idx[i]] for generic targets at -O2: GCC 14 kept it scalar, and Clang 23 used VGATHERDPS only when -march named a processor such as skylake or znver5. Both vendors’ guides advise against gathers where the addresses are predictable: Intel’s suggests loads and shuffles for sequential data, short strides and few elements, and notes a latency of about 50 cycles in Crestmont, where the gather is microcoded (Sections 15.16.4 and 4.1.9.6); AMD’s Zen 5 guide says that vector loads and shuffles give more load bandwidth when the indices are known ahead (Section 2.11.2).

VPGATHERDD gathers doublewords, VGATHERQPS takes 64-bit indices, and VSCATTERDPS is AVX-512’s store in the other direction.

In the optimization guide

What the optimization guide says about VGATHERDPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Where the layout of the data is known, vector loads and shuffles usually beat a gather.
• Gathers and scatters: Issue gathers early, gather many elements at once, use doubleword indices for 32-bit data and zero the destination first.
• Gathers and scatters: Gathers beat scalar loads on Skylake, while AMD lists them as microcode on Zen 3, Zen 4 and Zen 5.
• Gathers and scatters: GCC 14.2 builds no gathers when tuning for Zen 4 or Skylake, and LLVM none for Zen 3.

Crestmont and Gracemont

• Vectors and AVX2: Gathers are microcoded on these cores and take about 50 cycles.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: A gather is a load micro-op for each element plus a few more: LLVM’s models give an eight-element VPGATHERDD 12 micro-ops and a latency of 30 cycles, and the 16-element one of Sapphire Rapids 19 micro-ops.

Haswell and Broadwell

• Gathers: Haswell is the first core with gathers, and each one runs as many micro-ops; Broadwell runs them much faster.

Skylake to Cooper Lake

• Vectors on all parts: Gathers are faster than on Broadwell and beat a sequence of scalar loads unless they fetch only two elements or the data comes from memory rather than the caches.

Zen and Zen+

• Vectors and floating point: Gathers such as VPGATHERDD and VGATHERDPS are microcoded, 20 cycles with YMM registers in AMD’s spreadsheet, and GCC 14.2 builds none when tuning for znver1: vector loads and shuffles do better where the indices are known.

Zen 2

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, in AMD’s spreadsheet and LLVM’s model, so vector loads and shuffles beat them when the indices are known in advance.

Zen 3

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, and a register loaded in pieces is slower than one full-width load, so vector loads and shuffles beat both when the indices are known in advance.

Zen 4

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance, and a register loaded in pieces is slower than one full-width load.

Zen 5

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = mem.index.number
if x in (ymm1.number, ymm3.number):
    fault(UD)
if ymm1.number == ymm3.number:
    fault(UD)
for i in range(VL // 32):
    if ymm3.sd[i] < 0:
        a = mem.index.sd[i] * mem.scale
        ymm1.d[i] = load(mem.base + a, 32)
ymm3.write(0)
# ymm1 is zeroed from bit VL up

if mem.index.number == zmm1.number:
    fault(UD)
for i in range(VL // 32):
    if k1[i]:
        a = mem.index.sd[i] * mem.scale
        zmm1.d[i] = load(mem.base + a, 32)
k1.write(0)  # all of it
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-12

EVEX forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

gather

EVEX forms

write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGATHERDPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VBROADCASTI128
• VBROADCASTSD
• VBROADCASTSS
• VEXTRACTI128
• VGATHERDPD
• VGATHERQPD
• VGATHERQPS
• VINSERTI128
• VMOVNTDQA
• VMPSADBW
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VFNMSUB132SS
• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2

All 686 AVX10.1 instructions