VGATHERQPD

VGATHERQPD loads doubles from scattered addresses, each a base plus a signed 64-bit index times a scale of 1, 2, 4 or 8. Index and data have the same width, so 2, 4 or 8 indices in an XMM, YMM or ZMM register fetch as many doubles into a register of the same size, as for its integer twin VPGATHERQQ, whose page also shows whole pointers used as indices. VGATHERDPS explains the mask that selects elements and is cleared as they load, the #UD register rules and the faults it resumes after.

Recorded on Zen 5#

• Any alignment. With a scale of 1, vgatherqpd xmm4, qword ptr [base + xmm9*1], xmm11 read element 0 from 14 bytes above the base, an address that is not a multiple of 8, and kept element 1, whose mask had a clear sign bit.
• A mask register. vgatherqpd zmm1{k6}, qword ptr [base + zmm3*8] loaded the six elements that EEh, the low byte of K6, selects, from indices between -6 and 5, and left K6 zero.
• No arithmetic. The doubles arrived exactly as stored, and MXCSR stayed at 1F80h in all 5 cases; the SDM lists no floating-point exception for VGATHERQPD.

In compiled code#

For dd[i] = td[qidx[i]] with int64_t indices, Clang 23 at -O2 gathers four doubles per instruction with -march=x86-64-v4 and eight with znver5, setting the mask to all ones with KXNORW or KXNORB before each one; GCC 14 keeps the loop scalar. Both compile _mm512_i64gather_pd and its masked form, _mm512_mask_i64gather_pd, to VGATHERQPD on ZMM registers.

AMD’s Zen 5 latency spreadsheet lists VGATHERQPD as microcoded, with no latency, and its guide advises vector loads and shuffles instead of a gather when the indices are known in advance (Section 2.11.2).

In the optimization guide

What the optimization guide says about VGATHERQPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Where the layout of the data is known, vector loads and shuffles usually beat a gather.
• Gathers and scatters: Gathers beat scalar loads on Skylake, while AMD lists them as microcode on Zen 3, Zen 4 and Zen 5.

Crestmont and Gracemont

• Vectors and AVX2: Gathers are microcoded on these cores and take about 50 cycles.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: A gather is a load micro-op for each element plus a few more: LLVM’s models give an eight-element VPGATHERDD 12 micro-ops and a latency of 30 cycles, and the 16-element one of Sapphire Rapids 19 micro-ops.

Haswell and Broadwell

• Gathers: Haswell is the first core with gathers, and each one runs as many micro-ops; Broadwell runs them much faster.

Skylake to Cooper Lake

• Vectors on all parts: Gathers are faster than on Broadwell and beat a sequence of scalar loads unless they fetch only two elements or the data comes from memory rather than the caches.

Zen 2

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, in AMD’s spreadsheet and LLVM’s model, so vector loads and shuffles beat them when the indices are known in advance.

Zen 3

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, and a register loaded in pieces is slower than one full-width load, so vector loads and shuffles beat both when the indices are known in advance.

Zen 4

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance, and a register loaded in pieces is slower than one full-width load.

Zen 5

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = mem.index.number
if x in (ymm1.number, ymm3.number):
    fault(UD)
if ymm1.number == ymm3.number:
    fault(UD)
for i in range(VL // 64):
    if ymm3.sq[i] < 0:
        a = mem.index.sq[i] * mem.scale
        ymm1.q[i] = load(mem.base + a, 64)
ymm3.write(0)
# ymm1 is zeroed from bit VL up

if mem.index.number == zmm1.number:
    fault(UD)
for i in range(VL // 64):
    if k1[i]:
        a = mem.index.sq[i] * mem.scale
        zmm1.q[i] = load(mem.base + a, 64)
k1.write(0)  # all of it
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-12

EVEX forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

gather

EVEX forms

write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGATHERQPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VBROADCASTI128
• VBROADCASTSD
• VBROADCASTSS
• VEXTRACTI128
• VGATHERDPD
• VGATHERDPS
• VGATHERQPS
• VINSERTI128
• VMOVNTDQA
• VMPSADBW
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VFNMSUB213PD
• VFNMSUB213PH
• VFNMSUB213PS
• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4

All 686 AVX10.1 instructions