x86-64.net

Instruction

VGATHERQPS

Loads singles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.

Extensions
Forms
5 (2 VEX, 3 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VGATHERQPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VGATHERQPS xmm, vm64y, xmm VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256VEX.256.66.0F38.W0 93 /rAVX2
VGATHERQPS xmm, vm64x, xmm VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128VEX.128.66.0F38.W0 93 /rAVX2
VGATHERQPS ymm {k}, vm64z VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512EVEX.512.66.0F38.W0 93 /rAVX10.1 or AVX512F
VGATHERQPS xmm {k}, vm64x VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128EVEX.128.66.0F38.W0 93 /rAVX10.1 or AVX512F + AVX512VL
VGATHERQPS xmm {k}, vm64y VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256EVEX.256.66.0F38.W0 93 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGATHERQPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_i64gather_ps __m128 _mm_i64gather_ps(float const *m, __m128i i, const int s)

VGATHERQPS xmm, vm64x, xmm VEX.128 -mavx2

_mm_mask_i64gather_ps __m128 _mm_mask_i64gather_ps(__m128 a, float const *m, __m128i i, __m128 mask, const int s)

VGATHERQPS xmm, vm64x, xmm VEX.128 -mavx2

_mm_mmask_i64gather_ps __m128 _mm_mmask_i64gather_ps(__m128 v1_old, __mmask8 mask, __m128i index, void const *addr, const int scale)

VGATHERQPS xmm {k}, vm64x EVEX.128 -mavx512vl

_mm256_i64gather_ps __m128 _mm256_i64gather_ps(float const *m, __m256i i, const int s)

VGATHERQPS xmm, vm64y, xmm VEX.256 -mavx2

_mm256_mask_i64gather_ps __m128 _mm256_mask_i64gather_ps(__m128 a, float const *m, __m256i i, __m128 mask, const int s)

VGATHERQPS xmm, vm64y, xmm VEX.256 -mavx2

_mm256_mmask_i64gather_ps __m128 _mm256_mmask_i64gather_ps(__m128 v1_old, __mmask8 mask, __m256i index, void const *addr, const int scale)

VGATHERQPS xmm {k}, vm64y EVEX.256 -mavx512vl

_mm512_i64gather_ps __m256 _mm512_i64gather_ps(__m512i index, void const *addr, const int scale)

VGATHERQPS ymm {k}, vm64z EVEX.512 -mavx512f

_mm512_mask_i64gather_ps __m256 _mm512_mask_i64gather_ps(__m256 v1_old, __mmask8 mask, __m512i index, void const *addr, const int scale)

VGATHERQPS ymm {k}, vm64z EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX2GATHER

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.