Instruction
VGETEXPBF16
Extracts the unbiased exponent of each packed bfloat16 value as a bfloat16 number.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
VGETEXPBF16 returns the binary exponent of each bfloat16 value as a bfloat16, the largest integer e with 2^e no greater than |x|, 8, 16 or 32 per register. It is VGETEXPPS for bfloat16, and VGETMANTBF16 and VSCALEFBF16 are its partners for splitting a number and putting it back together. It belongs to AVX10.2; the opcode is 42h in EVEX map 6 with no prefix and W0, where VGETEXPPH has 66, and the source may be broadcast from 16 bits of memory. EVEX.vvvv must be 1111b.
Range and special inputs
A bfloat16 has the exponent range of a single, so the results run from -126 to 127, all exact. Denormals are read as zeros, as on VADDBF16’s page: a zero or a denormal gives -infinity, where VGETEXPPH reports a denormal’s true exponent. A NaN comes back quiet, and there are no exceptions and no MXCSR.
For infinities the AVX10.2 specification (revision 7.0) disagrees with itself. Its description defines the result as floor(log2(|x|)), which is +infinity for both, as Intel’s VGETEXPPS entry gives. Its routine, reworked in revision 3.0, returns +infinity only for +infinity: -infinity falls through to the branch that subtracts the bias from the exponent field, which would give 128.0.
In our builds
GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 compiles
_mm512_getexp_pbh to VGETEXPBF16. logbf on a __bf16 widens it with
a 16-bit shift, calls the library and narrows the result with
VCVTNEPS2BF16, even with -ffast-math. No
AVX10.2 processor appears in this site’s recorded cases.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VGETEXPBF16 xmm {k}{z}, xmm
VGETEXPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 | EVEX.128.NP.MAP6.W0 42 /r | AVX10.2 |
VGETEXPBF16 xmm {k}{z}, m128/m16bcst
VGETEXPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 | EVEX.128.NP.MAP6.W0 42 /r | AVX10.2 |
VGETEXPBF16 ymm {k}{z}, ymm
VGETEXPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 | EVEX.256.NP.MAP6.W0 42 /r | AVX10.2 |
VGETEXPBF16 ymm {k}{z}, m256/m16bcst
VGETEXPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 | EVEX.256.NP.MAP6.W0 42 /r | AVX10.2 |
VGETEXPBF16 zmm {k}{z}, zmm
VGETEXPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 | EVEX.512.NP.MAP6.W0 42 /r | AVX10.2 |
VGETEXPBF16 zmm {k}{z}, m512/m16bcst
VGETEXPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 | EVEX.512.NP.MAP6.W0 42 /r | AVX10.2 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Every bfloat16 works alike: 8, 16 and 32 bfloat16s in the xmm, ymm and zmm forms. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m16bcst, one bfloat16 from memory stands for every element of the last source.
Result bfloat16 i comes from bfloat16 i of xmm2. Result bfloat16s 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 16):
if k1[i]:
zmm1.bf16[i] = getexp(src2.bf16[i])
elif zeroing:
zmm1.bf16[i] = 0
# else: zmm1.bf16[i] keeps its value
# m16bcst: src2.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL upNot run on a processor: none of these processors has AVX10.2.
Operands
| Operand | Kind | Action |
|---|---|---|
VGETEXPBF16 xmm {k}{z}, xmm/m128/m16bcst VGETEXPBF16 ymm {k}{z}, ymm/m256/m16bcst VGETEXPBF16 zmm {k}{z}, zmm/m512/m16bcst | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm/m128/m16bcst, ymm/m256/m16bcst, zmm/m512/m16bcst | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking; always rounds to nearest even; denormal inputs read as zero; denormal results flushed to zero
- Memory forms
- embedded broadcast (tuple Full); memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VGETEXPBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_getexp_pbh
__m128bh _mm_getexp_pbh(__m128bh __A) |
|
_mm_mask_getexp_pbh
__m128bh _mm_mask_getexp_pbh(__m128bh __W, __mmask8 __U, __m128bh __A) |
|
_mm_maskz_getexp_pbh
__m128bh _mm_maskz_getexp_pbh(__mmask8 __U, __m128bh __A) |
|
_mm256_getexp_pbh
__m256bh _mm256_getexp_pbh(__m256bh __A) |
|
_mm256_mask_getexp_pbh
__m256bh _mm256_mask_getexp_pbh(__m256bh __W, __mmask16 __U, __m256bh __A) |
|
_mm256_maskz_getexp_pbh
__m256bh _mm256_maskz_getexp_pbh(__mmask16 __U, __m256bh __A) |
|
_mm512_getexp_pbh
__m512bh _mm512_getexp_pbh(__m512bh __A) |
|
_mm512_mask_getexp_pbh
__m512bh _mm512_mask_getexp_pbh(__m512bh __W, __mmask32 __U, __m512bh __A) |
|
_mm512_maskz_getexp_pbh
__m512bh _mm512_maskz_getexp_pbh(__mmask32 __U, __m512bh __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX10_2_BF16_128 | AVX10.2 | Nova Lake, Diamond Rapids |
AVX10_2_BF16_256 | Same as AVX10_2_BF16_128 | Same as AVX10_2_BF16_128 |
AVX10_2_BF16_512 | Same as AVX10_2_BF16_128 | Same as AVX10_2_BF16_128 |
More AVX10.2 instructions
- VCVTTPS2UQQS
- VCVTTSD2SIS
- VCVTTSD2USIS
- VCVTTSS2SIS
- VCVTTSS2USIS
- VDIVBF16
- VDPPHPS
- VFMADD132BF16
- VFMADD213BF16
- VFMADD231BF16
- VFMSUB132BF16
- VFMSUB213BF16
- VFMSUB231BF16
- VFNMADD132BF16
- VFNMADD213BF16
- VFNMADD231BF16
- VFNMSUB132BF16
- VFNMSUB213BF16
- VFNMSUB231BF16
- VFPCLASSBF16
- VGETMANTBF16
- VMAXBF16
- VMINBF16
- VMINMAXBF16
- VMINMAXPD
- VMINMAXPH
- VMINMAXPS
- VMINMAXSD
- VMINMAXSH
- VMINMAXSS
- VMOVD
- VMOVW
- VMPSADBW
- VMULBF16
- VPDPBSSD
- VPDPBSSDS
- VPDPBSUD
- VPDPBSUDS
- VPDPBUUD
- VPDPBUUDS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.