VGETEXPPH

VGETEXPPH returns the binary exponent of each half as a half, the largest integer e with 2^e no greater than |x|, 32 of them per zmm register. It is VGETEXPPS for halves, and that page covers the rule, the special inputs (a zero gives -infinity, an infinity +infinity, a NaN itself, made quiet) and the use with VGETMANTPH and VSCALEFPH, which split a number and put it back together. The opcode is 42h in EVEX map 6 with the 66 prefix: map 6 repeats the opcodes of the 0F38 map, where VGETEXPPS has the same byte. VADDPH covers the format and the CPUID bits.

Small range, every denormal#

The results are few: from 15 for the largest finite halves down to -14 for the smallest normal one, and on to -24 for the smallest denormal, 0001h, since a denormal is normalized first and reported with DE. Every one of these integers is exact as a half. Unlike VGETEXPPS, VGETEXPPH has no DAZ case: FP16 instructions ignore MXCSR.DAZ (Intel’s optimization manual, Section 18.5.4), so a denormal always gives its true exponent, never -infinity. The 512-bit register form takes {sae} to report no flags.

Intel’s optimization manual explains why that matters for halves (Section 18.7): with so narrow a range, denormal inputs are likely in a vectorized FP16 math library, and VGETEXPPH and VGETMANTPH let a logarithm treat them in the main path, as log(x) = VGETEXP(x) × log 2 + log(VGETMANT(x, 8)), with no branch.

In our builds#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 -mavx512fp16 emit VGETEXPPH for _mm512_getexp_ph. logbf on a _Float16, even with -ffast-math, converts it with VCVTSH2SS, calls the library and narrows the result with VCVTSS2SH. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VGETEXPPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.f16[i] = getexp(src2.f16[i])
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGETEXPPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMSUB213SD
• VFNMSUB213SH
• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2

All 686 AVX10.1 instructions