VGETEXPSD

VGETEXPSD returns the binary exponent of the low double of its second source as a double, floor(log2(|x|)), and copies bits 127:64 from the first source. It is the scalar form of VGETEXPPD, whose page gives the range: -1022 to 1023 for normal doubles, and down to -1074 for denormals, which it normalizes first, with MXCSR’s DE flag. VGETEXPPS lists the special inputs: zero gives -infinity, an infinity +infinity, and a NaN comes back as itself, quieted. The EVEX encoding adds a write mask on the one element, {sae} and xmm16 to xmm31, and clears the register from bit 128 up. VGETEXPSS is the single-precision form, and VGETMANTSD returns the matching significand.

Recorded on Zen 5#

• Masked off. vgetexpsd xmm1{k6}, xmm2, xmm3, {sae}, with bit 0 of K6 clear, kept the low double of XMM1, took bits 127:64 from XMM2 and cleared bits 511:128. The signaling NaN in XMM3 set no flag.
• A quiet NaN. With zeroing and bit 0 of K5 set, the quiet NaN 7FF8000000012345h from memory came back unchanged, and MXCSR kept its flags.

In compiled code#

At -O2 with -march=x86-64-v4, even with -ffast-math, GCC 14 and Clang 23 call the library for logb and ilogb. VGETEXPSD comes from _mm_getexp_sd(a, b), which both compile to one VGETEXPSD with a as the first source, and from its masked and {sae} variants.

AMD’s Zen 5 latency spreadsheet gives one macro-op and 3 cycles, two per cycle on pipes FP2 and FP3, as for the packed forms.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f64[0] = getexp(src3.f64[0])
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {sae}: no exception flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGETEXPSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMSUB213SS
• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS

All 686 AVX10.1 instructions