VGETEXPSH

VGETEXPSH returns the binary exponent of the low half of its second source, floor(log2|x|), as a half, and copies bits 127:16 from the first source, clearing the bits above 127. It is the scalar form of VGETEXPPH, whose page gives the range of results, 15 down to -24 for the smallest denormal, explains why FP16 has no DAZ case, and links VGETEXPPS for the special inputs: a zero gives -infinity, an infinity +infinity, a NaN itself, quiet. The encoding is 43h with the 66 prefix in EVEX map 6, where VGETEXPSS has the same byte in 0F38; it takes a write mask on the low half, {sae} and a two-byte memory operand. Intel’s entry lists invalid and denormal as its exceptions. VADDPH covers the format and the CPUID bits.

With the mantissa#

VGETEXPSH pairs with VGETMANTSH: the first gives the exponent and the second the significand, and VSCALEFSH puts them back together. Intel’s optimization manual builds a logarithm from the two as log(x) = VGETEXP(x) × log 2 + log(VGETMANT(x, 8)), which handles denormal and special inputs in the main path; for halves, with their narrow range, it expects denormal inputs to be common (Section 18.7).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 emit VGETEXPSH for _mm_getexp_sh(a, b), as vgetexpsh xmm0, xmm0, xmm1. C’s logbf and ilogbf on a _Float16 value convert it with VCVTSH2SS and call the library, also with -ffast-math; for logbf the result is narrowed again with VCVTSS2SH.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VGETEXPSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f16[0] = getexp(src3.f16[0])
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {sae}: no exception flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGETEXPSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMSUB231PD
• VFNMSUB231PH
• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD

All 686 AVX10.1 instructions