x86-64.net

Instruction

VGETEXPSS

Extracts the unbiased exponent of the low single of the second source as a floating-point number; the other elements come from the first source.

Extensions
Forms
2 (2 EVEX)
Data
Intel XED v2026.08.23

VGETEXPSS returns the binary exponent of the low single of its second source as a single, floor(log2(|x|)), and copies bits 127:32 from the first source. It is the scalar form of VGETEXPPS, whose page gives the special inputs, zero to -infinity, an infinity to +infinity and a NaN to itself, quieted, and the pairing with VGETMANT and VSCALEF. A normal single gives -126 to 127; a denormal is normalized first and gives -127 down to -149, with DE, unless DAZ makes it a zero. The EVEX encoding adds a write mask on the one element, {sae} and xmm16 to xmm31. VGETEXPSD is the double-precision form, and VGETMANTSS the matching significand.

Recorded on Zen 5

  • One register three times. In vgetexpss xmm5{k2}, xmm5, xmm5, {sae}, 2.0 became 1.0 and the three singles above it stayed.
  • A signaling NaN. FF800001h from memory came back quieted as FFC00001h, sign and payload kept, and set IE in MXCSR; bits 127:32 came from XMM8, the first source.

In compiled code

At -O2 with -march=x86-64-v4, even with -ffast-math, GCC 14 and Clang 23 call the library for logbf. _mm_getexp_ss(a, b) compiles to one VGETEXPSS with a as the first source, in both.

AMD’s Zen 5 latency spreadsheet gives one macro-op and 3 cycles, on pipes FP2 and FP3.

Forms

Every encoding of VGETEXPSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VGETEXPSS xmm {k}{z}, xmm, xmm, {sae} VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512EVEX.LIG.66.0F38.W0 43 /rAVX10.1 or AVX512F
VGETEXPSS xmm {k}{z}, xmm, m32 VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512EVEX.LIG.66.0F38.W0 43 /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm {k}{z}, xmm, xmm, {sae}xmm {k}{z}, xmm, m32
Skylake-SP, Ice Lake8 / 1p0114 / 1p01
Sapphire Rapids4 / 0.5p0111 / 0.5p01
Zen 43 / 0.5FP2 FP310 / 0.5FP2 FP3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm2.
VGETEXPSS: the low elementResult single 0 is computed from single 0 of xmm3; singles 3 to 1 are those of xmm2. Result singles 3 to 0: a3, a2, a1, r0.0123xmm2a1k1r0a1a2a3xmm10123xmm3or m32b

The write mask k1 applies to the low single: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result single 0 is computed from single 0 of xmm3; singles 3 to 1 are those of xmm2. Result singles 3 to 0: a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f32[0] = getexp(src3.f32[0])
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {sae}: no exception flags
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VGETEXPSS xmm {k}{z}, xmm, xmm/m32, {sae}
xmmexplicitwrite (masked)
{k}explicitread (write mask)
xmmexplicitread
xmm/m32explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms
write masking; follows MXCSR
Memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGETEXPSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_getexp_round_ss __m128 _mm_getexp_round_ss(__m128 A, __m128 B, const int R)

VGETEXPSS xmm, xmm, xmm, {sae} EVEX.LIG -mavx512f

_mm_getexp_ss __m128 _mm_getexp_ss(__m128 __A, __m128 __B)

VGETEXPSS xmm, xmm, xmm EVEX.LIG -mavx512f

_mm_mask_getexp_round_ss __m128 _mm_mask_getexp_round_ss(__m128 W, __mmask8 U, __m128 A, __m128 B, const int R)

VGETEXPSS xmm {k}, xmm, xmm, {sae} EVEX.LIG -mavx512f

_mm_mask_getexp_ss __m128 _mm_mask_getexp_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)

VGETEXPSS xmm {k}, xmm, xmm EVEX.LIG -mavx512f

_mm_maskz_getexp_round_ss __m128 _mm_maskz_getexp_round_ss(__mmask8 U, __m128 A, __m128 B, const int R)

VGETEXPSS xmm {k}{z}, xmm, xmm, {sae} EVEX.LIG -mavx512f

_mm_maskz_getexp_ss __m128 _mm_maskz_getexp_ss(__mmask8 __U, __m128 __A, __m128 __B)

VGETEXPSS xmm {k}{z}, xmm, xmm EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX512F_SCALAR

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2C, page 5-387 (VGETEXPSS)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.