Instruction
VGETMANTBF16
Extracts the normalized mantissa of each packed bfloat16 value, with the interval and sign handling chosen by an immediate.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
VGETMANTBF16 returns the significand of each bfloat16 value, scaled into an interval that bits 1:0 of the immediate choose, with bits 3:2 deciding the sign or turning negative inputs into the default NaN. It is VGETMANTPS for bfloat16, and that page has the table of both fields; VGETEXPBF16 returns the exponent that goes with it. It belongs to AVX10.2: the opcode is 26h in map 0F3A with the F2 prefix and W0, where VGETMANTPH has no prefix and VGETMANTPS 66, and the source may be broadcast from 16 bits of memory.
Seven bits of significand
A bfloat16 has 7 fraction bits, so VGETMANTBF16 returns one of 128 significands in the chosen interval, and the instruction never rounds: it replaces the exponent and keeps the fraction. Like the other bfloat16 instructions, it raises no exceptions and leaves MXCSR alone, as VADDBF16’s page explains. Denormals are read as zeros: the specification’s routine (revision 7.0) clears a denormal’s fraction, so with the interval from 1 to 2 a positive denormal gives 1.0, as +0 does, where VGETMANTPH, which ignores DAZ, returns its real significand. A logarithm built from VGETEXP and VGETMANT, as VGETEXPPH’s page shows for halves, therefore sees every denormal as a zero.
In our builds
GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 compiles
_mm512_getmant_pbh(x, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_src) to
vgetmantbf16 zmm0, zmm0, 0; its header builds the immediate as the
sign field shifted left by 2 joined with the interval. No C function
maps to it. No AVX10.2 processor appears in this site’s recorded cases.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VGETMANTBF16 xmm {k}{z}, xmm, imm8
VGETMANTBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512 | EVEX.128.F2.0F3A.W0 26 /r ib | AVX10.2 |
VGETMANTBF16 xmm {k}{z}, m128/m16bcst, imm8
VGETMANTBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 | EVEX.128.F2.0F3A.W0 26 /r ib | AVX10.2 |
VGETMANTBF16 ymm {k}{z}, ymm, imm8
VGETMANTBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512 | EVEX.256.F2.0F3A.W0 26 /r ib | AVX10.2 |
VGETMANTBF16 ymm {k}{z}, m256/m16bcst, imm8
VGETMANTBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 | EVEX.256.F2.0F3A.W0 26 /r ib | AVX10.2 |
VGETMANTBF16 zmm {k}{z}, zmm, imm8
VGETMANTBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512 | EVEX.512.F2.0F3A.W0 26 /r ib | AVX10.2 |
VGETMANTBF16 zmm {k}{z}, m512/m16bcst, imm8
VGETMANTBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 | EVEX.512.F2.0F3A.W0 26 /r ib | AVX10.2 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Every bfloat16 works alike: 8, 16 and 32 bfloat16s in the xmm, ymm and zmm forms. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m16bcst, one bfloat16 from memory stands for every element of the last source.
Result bfloat16 i comes from bfloat16 i of xmm2. Result bfloat16s 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 16):
if k1[i]:
a = src2.bf16[i]
zmm1.bf16[i] = getmant(a, imm8)
elif zeroing:
zmm1.bf16[i] = 0
# else: zmm1.bf16[i] keeps its value
# imm8[1:0]: [1, 2), [1/2, 2), [1/2, 1), [3/4, 3/2); bit 2: no sign; bit 3: negative gives NaN
# m16bcst: src2.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL upNot run on a processor: none of these processors has AVX10.2.
Operands
| Operand | Kind | Action |
|---|---|---|
VGETMANTBF16 xmm {k}{z}, xmm/m128/m16bcst, imm8 VGETMANTBF16 ymm {k}{z}, ymm/m256/m16bcst, imm8 VGETMANTBF16 zmm {k}{z}, zmm/m512/m16bcst, imm8 | ||
xmm, ymm, zmm | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm/m128/m16bcst, ymm/m256/m16bcst, zmm/m512/m16bcst | explicit | read |
imm8 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
AVX512-E4
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking; denormal inputs read as zero; denormal results flushed to zero
- Memory forms
- embedded broadcast (tuple Full); memory fault suppression
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VGETMANTBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_getmant_pbh
__m128bh _mm_getmant_pbh(__m128bh __A, const int __B, const int __C) |
|
_mm_mask_getmant_pbh
__m128bh _mm_mask_getmant_pbh(__m128bh __W, __mmask8 __U, __m128bh __A, const int __B, const int __C) |
|
_mm_maskz_getmant_pbh
__m128bh _mm_maskz_getmant_pbh(__mmask8 __U, __m128bh __A, const int __B, const int __C) |
|
_mm256_getmant_pbh
__m256bh _mm256_getmant_pbh(__m256bh __A, const int __B, const int __C) |
|
_mm256_mask_getmant_pbh
__m256bh _mm256_mask_getmant_pbh(__m256bh __W, __mmask16 __U, __m256bh __A, const int __B, const int __C) |
|
_mm256_maskz_getmant_pbh
__m256bh _mm256_maskz_getmant_pbh(__mmask16 __U, __m256bh __A, const int __B, const int __C) |
|
_mm512_getmant_pbh
__m512bh _mm512_getmant_pbh(__m512bh __A, const int __B, const int __C) |
|
_mm512_mask_getmant_pbh
__m512bh _mm512_mask_getmant_pbh(__m512bh __W, __mmask32 __U, __m512bh __A, const int __B, const int __C) |
|
_mm512_maskz_getmant_pbh
__m512bh _mm512_maskz_getmant_pbh(__mmask32 __U, __m512bh __A, const int __B, const int __C) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX10_2_BF16_128 | AVX10.2 | Nova Lake, Diamond Rapids |
AVX10_2_BF16_256 | Same as AVX10_2_BF16_128 | Same as AVX10_2_BF16_128 |
AVX10_2_BF16_512 | Same as AVX10_2_BF16_128 | Same as AVX10_2_BF16_128 |
More AVX10.2 instructions
- VCVTTSD2SIS
- VCVTTSD2USIS
- VCVTTSS2SIS
- VCVTTSS2USIS
- VDIVBF16
- VDPPHPS
- VFMADD132BF16
- VFMADD213BF16
- VFMADD231BF16
- VFMSUB132BF16
- VFMSUB213BF16
- VFMSUB231BF16
- VFNMADD132BF16
- VFNMADD213BF16
- VFNMADD231BF16
- VFNMSUB132BF16
- VFNMSUB213BF16
- VFNMSUB231BF16
- VFPCLASSBF16
- VGETEXPBF16
- VMAXBF16
- VMINBF16
- VMINMAXBF16
- VMINMAXPD
- VMINMAXPH
- VMINMAXPS
- VMINMAXSD
- VMINMAXSH
- VMINMAXSS
- VMOVD
- VMOVW
- VMPSADBW
- VMULBF16
- VPDPBSSD
- VPDPBSSDS
- VPDPBSUD
- VPDPBSUDS
- VPDPBUUD
- VPDPBUUDS
- VPDPWSUD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.