VGETMANTPD

VGETMANTPD returns the significand of each double, scaled into an interval that the immediate picks, and VGETEXPPD the exponent. It is the double form of VGETMANTPS, whose page tables the two immediate fields, bits 1:0 for the interval and bits 3:2 for the sign rule, and shows how the special inputs come out.

Recorded on Zen 5#

• Interval 1, [1/2, 2). Under 09h, 2147483647.5, which is 1.9999999995 times 2^30, kept its significand, since 30 is even, while 1e-300, 1.339 times 2^-997, came back halved as 0.6697.
• Negative inputs. The same immediate’s sign rule turned -2147483648 into the default NaN, FFF8000000000000h. MXCSR was 1E40h, which leaves the invalid-operation exception unmasked, but {sae} suppressed it: no #XM, and MXCSR kept its value. Under 0Dh, without {sae} and with IE masked, -1.0 gave the NaN and set IE.
• The upper bits. As for singles, Zen 5 ignored bits 7:4: 1Ch acted as 0Ch and turned -1.0 into the NaN with IE.
• Other rules. Under 05h, whose sign rule clears the sign, -1.0 gave 1.0, and under F3h, interval 3 with the upper bits again ignored, +infinity gave 1.0.

In compiled code#

GCC 14 and Clang 23 at -O2 call frexp and logb even with -ffast-math and -march=x86-64-v4 or znver5. VGETMANTPD comes from the intrinsics: with _MM_MANT_NORM_p5_1 and _MM_MANT_SIGN_src, _mm512_getmant_pd is immediate 02h, the interval that frexp returns, and _mm512_getmant_round_pd with _MM_FROUND_NO_EXC adds {sae}.

AMD’s Zen 5 latency spreadsheet gives VGETMANTPD 3 cycles and two per cycle on pipes FP2 and FP3, as VGETMANTPS.

In the optimization guide

What the optimization guide says about VGETMANTPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f64[i]
        zmm1.f64[i] = getmant(a, imm8)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# imm8[1:0]: [1, 2), [1/2, 2), [1/2, 1), [3/4, 3/2); bit 2: no sign; bit 3: negative gives NaN
# m64bcst: src2.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGETMANTPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMSUB231PS
• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS

All 686 AVX10.1 instructions