VGETMANTPH

VGETMANTPH returns the significand of each half, scaled into an interval that bits 1:0 of the immediate choose, with bits 3:2 deciding the sign or turning negative inputs into the default NaN. It is VGETMANTPS for halves, and that page has the table of both fields and the special inputs: zero and infinity give 1.0 with their sign, a NaN comes back quiet. VGETEXPPH returns the exponent that goes with it, and VADDPH covers the format and the CPUID bits.

Encoding#

Unlike most FP16 instructions, VGETMANTPH stays in the 0F3A map: opcode 26h with no prefix, where VGETMANTPS is the same byte with 66. The other FP16 instructions with an immediate do the same: VFPCLASSPH, VCMPPH, VRNDSCALEPH and VREDUCEPH. Intel’s manual requires imm8 bits 7:4 to be zero.

Denormals and the logarithm#

FP16 instructions ignore MXCSR.DAZ (Intel’s optimization manual, Section 18.5.4), so a denormal half is always normalized, reported with DE, and returns its real significand, never the 1.0 a zero gives. The same manual’s recipe for logarithms (Section 18.7) uses imm8 8: the interval from 1 up to 2 for positive inputs and the default NaN for negative ones, which leaves the special cases to fall out of the main path: log(x) = VGETEXP(x) × log 2 + log(VGETMANT(x, 8)).

In our builds#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 -mavx512fp16 compile _mm512_getmant_ph(x, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_nan) to vgetmantph zmm0, zmm0, 8, the manual’s immediate. Nothing in C maps to it: frexpf on a _Float16 stays a library call, even with -ffast-math. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VGETMANTPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.f16[i]
        zmm1.f16[i] = getmant(a, imm8)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# imm8[1:0]: [1, 2), [1/2, 2), [1/2, 1), [3/4, 3/2); bit 2: no sign; bit 3: negative gives NaN
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGETMANTPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMSUB231SD
• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD

All 686 AVX10.1 instructions