VGETMANTPS

VGETMANTPS returns the significand of each single, scaled into an interval that the immediate picks; VGETEXPPS returns the exponent, and its page shows how the two split a number and how VSCALEFPS puts it back together. The immediate has two fields:

Interval 1 leaves an even exponent behind, so that x is the result times a power of 4, which suits square roots. Intel’s optimization manual builds log2(x) on imm8 8, interval 0 with negative inputs turned into NaN, and divides through VGETMANT(a, 0) / VGETMANT(b, 0), which stays in [1, 2) for every input that is not a NaN (Sections 17.15.2 and 17.15.5).

Special inputs, as Zen 5 recorded them#

• Zero and infinity give 1.0 with their sign: -0 gave -1.0 and +infinity 1.0. With bits 3:2 = 2 or 3, -infinity gives the NaN, but -0 still gives -1.0, or 1.0 when bit 2 clears the sign.
• A denormal is normalized first: 007FFFFFh gave 1.9999998 (3FFFFFFEh) and set DE. Under DAZ it counts as zero and gives 1.0, with no DE.
• A NaN comes back quiet, and an SNaN raises IE. With IE unmasked, vectors holding an SNaN and negative inputs raised #XM under imm8 0Ah and 0Bh.
• {sae}, on the 512-bit register form, suppresses that: such a vector under imm8 0Dh, with every exception unmasked, gave the NaNs and left MXCSR unchanged.

Intel’s manual says that imm8 bits 7:4 must be zero. Zen 5 ignores them: F3h acted as 3 and 1Ch as 0Ch.

Neither GCC 14 nor Clang 23 at -O2 turns frexpf into VGETMANTPS, even with -ffast-math and -march=x86-64-v4. The intrinsics _mm512_getmant_ps and kin give it, taking the interval and the sign rule as two enum arguments.

In the optimization guide

What the optimization guide says about VGETMANTPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f32[i]
        zmm1.f32[i] = getmant(a, imm8)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# imm8[1:0]: [1, 2), [1/2, 2), [1/2, 1), [3/4, 3/2); bit 2: no sign; bit 3: negative gives NaN
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGETMANTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFNMSUB231SH
• VFNMSUB231SS
• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH

All 686 AVX10.1 instructions