VGETMANTSH

VGETMANTSH returns the significand of the low half of its second source, scaled into the interval that bits 1:0 of the immediate choose, with bits 3:2 deciding the sign or turning a negative input into the default NaN; bits 127:16 come from the first source and the bits above 127 are cleared. It is the scalar form of VGETMANTPH, whose page links the table of both immediate fields on VGETMANTPS’s and explains why a denormal half always yields its real significand. The opcode is 27h in the 0F3A map with no prefix, where VGETMANTSS has 66, and it takes a write mask on the low half, {sae} and a two-byte memory operand. Intel’s entry lists invalid and denormal. VADDPH covers the format and the CPUID bits.

The logarithm’s other half#

VGETEXPSH gives the exponent that goes with the significand, and the two split a half x into 2^e times m with m in the chosen interval. Intel’s optimization manual uses the immediate 8, the interval from 1 up to 2 with the default NaN for negative inputs, in its recipe log(x) = VGETEXP(x) × log 2 + log(VGETMANT(x, 8)), where the NaN takes care of the inputs a logarithm rejects without a branch (Section 18.7).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile _mm_getmant_sh(a, b, _MM_MANT_NORM_1_2, _MM_MANT_SIGN_nan) to vgetmantsh xmm0, xmm0, xmm1, 8, the manual’s immediate. No C function maps to it: as VGETMANTPH’s page notes, frexpf on a half stays a library call, also with -ffast-math, and so do logbf and ilogbf, as VGETEXPSH’s page shows.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VGETMANTSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f16[0] = getmant(src3.f16[0], imm8)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {sae}: no exception flags
# imm8[1:0]: [1, 2), [1/2, 2), [1/2, 1), [3/4, 3/2); bit 2: no sign; bit 3: negative gives NaN
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGETMANTSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFPCLASSPD
• VFPCLASSPH
• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD

All 686 AVX10.1 instructions