VGF2P8AFFINEINVQB

VGF2P8AFFINEINVQB is GF2P8AFFINEINVQB in VEX and EVEX encodings: each byte is replaced by its inverse in GF(2^8), multiplied by the 8-by-8 bit matrix in the matching quadword of the second source, and XORed with the immediate. That page covers the field, the inverse and AES’s S-box, and GF2P8AFFINEQB the layout of the matrix. The new encodings add a separate destination, zeroed above the vector length, a memory operand at any alignment, and wider vectors:

• The VEX forms, on xmm and ymm registers, need GFNI and AVX, not AVX-512.
• The EVEX forms need GFNI with AVX512VL below 512 bits, AVX512F at 512 bits, or AVX10.1. Their write mask selects bytes, but their broadcast repeats a quadword: one matrix for every group of eight bytes.
• The EVEX forms belong to exception class E4NF, without fault suppression: a memory operand is read in full whatever the mask.

On Zen 5#

vgf2p8affineinvqb zmm17, zmm30, qword bcst [mem], 0 broadcast the identity matrix 0102040810204080h to all eight quadwords, which leaves the plain inverse: 02h became 8Dh, 80h became 83h, FFh became 1Ch, 53h and CAh swapped, and 00h stayed 00h, as the SDM’s table lists. With AES’s matrix F1E3C78F1F3E7CF8h in its third quadword and an immediate of 63h, {evex} vgf2p8affineinvqb zmm1, zmm2, zmmword ptr [mem], 0x63 turned 00h, 01h, 53h and FFh into 63h, 7Ch, EDh and 16h, their S-box values in FIPS-197; a zero quadword in the matrix gave 63h for each of its bytes, the immediate alone.

In our builds#

GCC 14 and Clang 23 at -O2 emit it only for the intrinsics, which need -mgfni on top of -mavx2 or an x86-64 level: both reject them with -march=x86-64-v4 alone and accept them with -march=znver5. An S-box loop over _mm256_gf2p8affineinv_epi64_epi8 keeps the VEX form even with -march=x86-64-v4 -mgfni; the _mm512_ and masked intrinsics give EVEX. Both compilers keep the matrix in a register: GCC loads it as a full vector constant, Clang with a VPBROADCASTQ of one quadword.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike a latency of 3 cycles, two per cycle on pipes FP1 and FP2.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:                    # 1 without a write mask
        a = src3.q[i // 8]       # the matrix of byte i
        x = gf2p8inv(zmm2.b[i])  # the inverse; 0 for 0
        r = 0
        for j in range(8):       # bit j: row 7 - j
            row = a >> 8 * (7 - j) & 0xFF
            r |= popcount(row & x) % 2 << j
        zmm1.b[i] = r ^ imm8
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGF2P8AFFINEINVQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More GFNI instructions

• GF2P8AFFINEINVQB
• GF2P8AFFINEQB
• GF2P8MULB
• VGF2P8AFFINEQB
• VGF2P8MULB

More AVX10.1 instructions

• VFPCLASSPS
• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS

All 686 AVX10.1 instructions