VGF2P8AFFINEQB

VGF2P8AFFINEQB multiplies every byte by an 8-by-8 bit matrix and XORs in the immediate: the VEX and EVEX forms of GF2P8AFFINEQB, whose page covers how the matrix is read and what compilers build from it. The VEX forms need GFNI and AVX, at both widths; the EVEX forms need GFNI with AVX512F, plus AVX512VL below 512 bits, or AVX10.1. All take a separate destination and memory at any alignment, and clear the register above the vector length. EVEX adds a write mask per byte and a matrix broadcast from one quadword of memory, the usual case of one transform for every byte.

A matrix per quadword#

The matrix stays a quadword of the second source for the 8 bytes in the same position, so a wide register can hold a different one for each quadword. On Zen 5, the recorded vgf2p8affineqb ymm8, ymm15, ymm0, 0x80 used the identity in the first quadword, the bit reversal in the second and all ones in the third, which puts the parity of each byte into all eight bits: after the XOR with 80h, 5Fh, with six bits set, became 80h and 89h, with three, 7Fh. vgf2p8affineqb ymm17{k4}, ymm30, qword bcst [mem], 0xff broadcast the all-ones matrix and wrote only the bytes k4 selects: 53h became FFh in byte 3, while byte 2, its mask bit clear, kept 49h.

In compiled code#

GFNI is in neither x86-64-v3 nor v4, so our builds at -O2 add -mgfni. Clang 23 then compiles the byte shifts and rotates by a constant and the bit reversal loop over fixed-size uint8_t arrays to one VPBROADCASTQ of the matrix and one VGF2P8AFFINEQB per 32 bytes, on ymm registers at both levels. GCC 14 emits it only for the intrinsics, shifting words and masking for the shifts. For _mm512_gf2p8affine_epi64_epi8 with a matrix from _mm512_set1_epi64, Clang reads it as a broadcast quadword, while GCC loads a full 64-byte constant.

AMD’s latency spreadsheet for Zen 5 gives the VEX row and the EVEX row the legacy form’s figures: one macro-op, a latency of 3 cycles and two per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:                    # 1 without a write mask
        a = src3.q[i // 8]       # the matrix of byte i
        x = zmm2.b[i]
        r = 0
        for j in range(8):       # bit j: row 7 - j
            row = a >> 8 * (7 - j) & 0xFF
            r |= popcount(row & x) % 2 << j
        zmm1.b[i] = r ^ imm8
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGF2P8AFFINEQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More GFNI instructions

• GF2P8AFFINEINVQB
• GF2P8AFFINEQB
• GF2P8MULB
• VGF2P8AFFINEINVQB
• VGF2P8MULB

More AVX10.1 instructions

• VFPCLASSSD
• VFPCLASSSH
• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD

All 686 AVX10.1 instructions