x86-64.net

Instruction

VGF2P8AFFINEQB

Applies an affine transformation to each byte, given by an 8x8 bit matrix from the second source and an immediate constant.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VGF2P8AFFINEQB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VGF2P8AFFINEQB xmm, xmm, xmm, imm8 VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8VEX.128.66.0F3A.W1 CE /r ibGFNI + AVX
VGF2P8AFFINEQB xmm, xmm, m128, imm8 VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8VEX.128.66.0F3A.W1 CE /r ibGFNI + AVX
VGF2P8AFFINEQB ymm, ymm, ymm, imm8 VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8VEX.256.66.0F3A.W1 CE /r ibGFNI + AVX
VGF2P8AFFINEQB ymm, ymm, m256, imm8 VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8VEX.256.66.0F3A.W1 CE /r ibGFNI + AVX
VGF2P8AFFINEQB xmm {k}{z}, xmm, xmm, imm8 VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512EVEX.128.66.0F3A.W1 CE /r ibAVX10.1 + GFNI or GFNI + AVX512F + AVX512VL
VGF2P8AFFINEQB xmm {k}{z}, xmm, m128/m64bcst, imm8 VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512EVEX.128.66.0F3A.W1 CE /r ibAVX10.1 + GFNI or GFNI + AVX512F + AVX512VL
VGF2P8AFFINEQB ymm {k}{z}, ymm, ymm, imm8 VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512EVEX.256.66.0F3A.W1 CE /r ibAVX10.1 + GFNI or GFNI + AVX512F + AVX512VL
VGF2P8AFFINEQB ymm {k}{z}, ymm, m256/m64bcst, imm8 VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512EVEX.256.66.0F3A.W1 CE /r ibAVX10.1 + GFNI or GFNI + AVX512F + AVX512VL
VGF2P8AFFINEQB zmm {k}{z}, zmm, zmm, imm8 VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512EVEX.512.66.0F3A.W1 CE /r ibAVX10.1 + GFNI or GFNI + AVX512F
VGF2P8AFFINEQB zmm {k}{z}, zmm, m512/m64bcst, imm8 VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512EVEX.512.66.0F3A.W1 CE /r ibAVX10.1 + GFNI or GFNI + AVX512F

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VGF2P8AFFINEQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_gf2p8affine_epi64_epi8 __m128i _mm_gf2p8affine_epi64_epi8(__m128i A, __m128i B, const char I)

VGF2P8AFFINEQB xmm, xmm, xmm, imm8 VEX.128 -mgfni -mavxwith AVX enabled

_mm_mask_gf2p8affine_epi64_epi8 __m128i _mm_mask_gf2p8affine_epi64_epi8(__m128i S, __mmask16 U, __m128i A, __m128i B, const char I)

VGF2P8AFFINEQB xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx512bw -mavx512vl -mgfni

_mm_maskz_gf2p8affine_epi64_epi8 __m128i _mm_maskz_gf2p8affine_epi64_epi8(__mmask16 U, __m128i A, __m128i B, const char I)

VGF2P8AFFINEQB xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx512bw -mavx512vl -mgfni

_mm256_gf2p8affine_epi64_epi8 __m256i _mm256_gf2p8affine_epi64_epi8(__m256i A, __m256i B, const char I)

VGF2P8AFFINEQB ymm, ymm, ymm, imm8 VEX.256 -mavx -mgfni

_mm256_mask_gf2p8affine_epi64_epi8 __m256i _mm256_mask_gf2p8affine_epi64_epi8(__m256i S, __mmask32 U, __m256i A, __m256i B, const char I)

VGF2P8AFFINEQB ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx512bw -mavx512vl -mgfni

_mm256_maskz_gf2p8affine_epi64_epi8 __m256i _mm256_maskz_gf2p8affine_epi64_epi8(__mmask32 U, __m256i A, __m256i B, const char I)

VGF2P8AFFINEQB ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx512bw -mavx512vl -mgfni

_mm512_gf2p8affine_epi64_epi8 __m512i _mm512_gf2p8affine_epi64_epi8(__m512i A, __m512i B, const char I)

VGF2P8AFFINEQB zmm, zmm, zmm, imm8 EVEX.512 -mavx512f -mgfni

_mm512_mask_gf2p8affine_epi64_epi8 __m512i _mm512_mask_gf2p8affine_epi64_epi8(__m512i S, __mmask64 U, __m512i A, __m512i B, const char I)

VGF2P8AFFINEQB zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx512bw -mgfni

_mm512_maskz_gf2p8affine_epi64_epi8 __m512i _mm512_maskz_gf2p8affine_epi64_epi8(__mmask64 U, __m512i A, __m512i B, const char I)

VGF2P8AFFINEQB zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx512bw -mgfni

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX_GFNI

GFNI + AVX
CPUID.(EAX=07H,ECX=0):ECX[8] GFNI
CPUID.01H:ECX[28] AVX

Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest
AVX512_GFNI_128

AVX10.1 + GFNI
CPUID.(EAX=07H,ECX=0):ECX[8] GFNI
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

GFNI + AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[8] GFNI
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_GFNI_256

AVX10.1 + GFNI
CPUID.(EAX=07H,ECX=0):ECX[8] GFNI
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

GFNI + AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):ECX[8] GFNI
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_GFNI_512

AVX10.1 + GFNI
CPUID.(EAX=07H,ECX=0):ECX[8] GFNI
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

GFNI + AVX512F
CPUID.(EAX=07H,ECX=0):ECX[8] GFNI
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.