VINSERTF128

VINSERTF128 copies a ymm source to the destination and replaces one 128-bit half of the copy with 16 bytes from an xmm register or memory: the low half when bit 0 of the immediate is 0, the high half when it is

1. It does what VINSERTI128 does, and that page covers its uses (joining two halves, loading two rows, lane-wise code) and its EVEX successors. What sets it apart is that it needs only AVX, so it is the instruction that code for AVX alone has for building a ymm register out of xmm values.

Only bit 0 counts#

The cases recorded on Zen 5 used immediates with other bits set:

• vinsertf128 ymm4, ymm4, xmmword ptr [mem], 0x2A replaced the low half with the 16 bytes from memory and kept ymm4’s high half;
• vinsertf128 ymm8, ymm15, xmm0, 0x45 put xmm0 into the high half over a copy of ymm15’s low half.

Both cleared bits 256 to 511 of the destination’s zmm register, as a VEX instruction does.

In code for AVX#

With -mavx, GCC 14 and Clang 23 at -O2 emit VINSERTF128 wherever halves meet, for doubles and singles alike:

• _mm256_set_m128d(hi, lo) and a shuffle that joins the low halves of two vectors are vinsertf128 ymm0, ymm0, xmm1, 1;
• _mm256_set1_pd(x) is VMOVDDUP and a VINSERTF128 of xmm0 into itself, since the register form of VBROADCASTSD needs AVX2;
• setting element 0 of four doubles is, in GCC, VMOVSD into a copy of the low half and VINSERTF128 with an immediate of 0 to put it back; Clang uses VBLENDPS instead.

AMD’s Zen 5 guide lists the register and memory forms as one macro-op on the pipes FP1 and FP2 with a latency of 1 cycle, against 3 cycles for VPERM2F128, which can also join two halves.

In the optimization guide

What the optimization guide says about VINSERTF128, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Shuffles and lane crossing: Most 256-bit AVX instructions stay within 128-bit lanes, and loading each lane with VINSERTF128 avoids shuffles across them.

Crestmont and Gracemont

• Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Sandy Bridge and Ivy Bridge

• AVX, SSE and denormals: Moving data between a YMM register’s two 128-bit halves always costs one extra cycle: VINSERTF128, which does this, has a latency of 2 cycles against the 1 cycle of a shuffle or blend that stays within one half.

Zen and Zen+

• Vectors and floating point: VPERM2F128 is microcoded, three cycles in AMD’s spreadsheet and eight macro-ops in LLVM’s model, while VINSERTF128 and VEXTRACTF128, which move one 128-bit half, take a cycle; moving halves with them beats a full permute. sources differ

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

ymm1.write(ymm2.read())
ymm1.dq[imm8 & 1] = src3.dq[0]
# ymm1 is zeroed from bit 256 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-6

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VINSERTF128, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VCVTSI2SD
• VCVTSI2SS
• VCVTSS2SD
• VCVTSS2SI
• VCVTTPD2DQ
• VCVTTPS2DQ
• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU

All 253 AVX instructions