VINSERTF32X4

VINSERTF32X4 copies a YMM or ZMM source to the destination with one 128-bit block replaced by 16 bytes from an XMM register or memory, and writes the result under a mask of singles. It is VINSERTI32X4 under a floating-point name, and that page explains the immediate, bits 1:0 at 512 bits and bit 0 at 256; nothing is converted, so no SIMD exception can arise. Unmasked on YMM registers it does what VINSERTF128 does, and VEXTRACTF32X4 is the reverse.

Recorded on Zen 5#

• Only bits 1:0 count. vinsertf32x4 zmm14{k2}, zmm8, xmm29, 0x5c put XMM29 in block 0, since 5Ch ends in binary 00, and with F2C9h in K2 kept the singles of ZMM14 whose mask bits are clear.
• Zeroing at 256 bits. vinsertf32x4 ymm1{k2}{z}, ymm2, xmm3, 0x86 replaced the low block and, with C9h in the low byte of K2, wrote singles 0, 3, 6 and 7 and zeroed the other four.
• Memory source. vinsertf32x4 ymm0, ymm31, xmmword ptr [mem], 0x62 put the 16 bytes of memory in the low block and the high block of YMM31 above them.

In compiled code#

With GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, _mm512_insertf32x4 is VINSERTF32X4 in both, masked or not. Without a mask the element size makes no difference, and Clang uses VINSERTF32X4 for _mm512_inserti32x4 and _mm512_insertf64x2 too, while GCC keeps the names of the intrinsics. Building a ZMM register from four XMM ones takes GCC three VINSERTF32X4, and Clang two VINSERTF128 and a VINSERTF64X4. For a 16-byte load into block 3, Clang folds the load into the insert and GCC loads into a register first. _mm256_insertf32x4(a, b, 1) is the EVEX VINSERTF32X4 in GCC and the VEX VINSERTF128 in Clang.

AMD’s Zen 5 latency spreadsheet gives VINSERTF32X4 one cycle and two per cycle on pipes FP1 and FP2, as VINSERTI32X4.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & (VL // 128 - 1)  # the 128-bit block replaced
for i in range(VL // 32):
    if k1[i]:
        if i // 4 == x:
            zmm1.d[i] = src3.d[i % 4]
        else:
            zmm1.d[i] = zmm2.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VINSERTF32X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VFPCLASSSS
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS

All 686 AVX10.1 instructions