VINSERTF32X8

VINSERTF32X8 copies a ZMM source to the destination with its low or high 256 bits, chosen by bit 0 of the immediate, replaced by a YMM register or 32 bytes of memory, and writes the result under a mask of singles. It is VINSERTI32X8 under a floating-point name, with the same bits moved and the same AVX512DQ requirement, and that page sets it against VINSERTI64X4, which gives the same result unmasked. Nothing is converted or quieted, and no SIMD exception can arise.

Recorded on Zen 5#

• Source and destination in one register. In vinsertf32x8 zmm7{k4}, zmm12, ymm7, 0xe9, only bit 0 of E9h counted and put YMM7 in the high half: the selected singles 8, 10, 11, 13 and 14 received the old singles 0, 2, 3, 5 and 6 of ZMM7, so the YMM source was read before any element was written. In the low half the selected singles came from ZMM12 and the others kept ZMM7’s old values.
• Memory into the low half. With immediate 08h, bit 0 clear, vinsertf32x8 zmm24{k3}, zmm3, [mem], 0x8 put memory singles 0, 1, 3, 5, 6 and 7 where AAEBh, the low 16 bits of K3, selected them, and ZMM3’s singles 9, 11, 13 and 15 in the high half.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile the masked _mm512_mask_insertf32x8 and _mm512_maskz_insertf32x8 to VINSERTF32X8. Unmasked, GCC keeps VINSERTF32X8 for _mm512_insertf32x8(x, y, 1), also when it joins two __m256 halves, while Clang emits VINSERTF64X4. Inserting a vector loaded from memory into a copy of itself becomes a load and VINSERTF32X8 in GCC and one VBROADCASTF64X4 in Clang.

AMD’s Zen 5 latency spreadsheet gives VINSERTF32X8 one cycle and two per cycle on pipes FP1 and FP2, the same as VINSERTI32X8.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & 1  # the 256-bit block replaced
for i in range(16):
    if k1[i]:
        if i // 8 == x:
            zmm1.d[i] = src3.d[i % 8]
        else:
            zmm1.d[i] = zmm2.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VINSERTF32X8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD

All 686 AVX10.1 instructions