VINSERTF64X2

VINSERTF64X2 copies a YMM or ZMM source to the destination with one 128-bit block replaced by two doubles from an XMM register or memory, then writes the result under a mask of quadwords. It is VINSERTI64X2 under a floating-point name, and that page and VINSERTI32X4’s explain how the immediate picks the block; VINSERTF32X4 is the form with a mask of singles, and unmasked on YMM registers the result is that of AVX’s VINSERTF128. It came with AVX512DQ.

Recorded on Zen 5#

• Only the low immediate bits. Immediate 49h put the memory operand in the upper half of YMM7, by bit 0; 3Bh put it in block 3 of ZMM17, by bits 1:0, where K3 kept elements 2 and 4 of the old ZMM17.
• A block over itself. vinsertf64x2 zmm5{k3}, zmm5, xmm5, 8 replaced block 0 with XMM5, its own low bits, and changed nothing.
• Zero mask, nothing selected. With the low four bits of K1 clear, vinsertf64x2 ymm9{k1}{z}, ymm9, xmm14, 82h cleared the register.

In compiled code#

GCC 14 at -O2 with -march=x86-64-v4 compiles _mm512_insertf64x2 and _mm256_insertf64x2 to VINSERTF64X2, and uses it even for _mm256_set_m128d, the joining of two XMM values, where an AVX VINSERTF128 would do with a VEX encoding one byte shorter. Clang 23 uses VINSERTF32X4 for the ZMM intrinsic, with the memory operand folded in where GCC loads it first, and VINSERTF128 for the YMM forms.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP1 or FP2 and one cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & (VL // 128 - 1)  # the 128-bit block replaced
for i in range(VL // 64):
    if k1[i]:
        if i // 2 == x:
            zmm1.q[i] = src3.q[i % 2]
        else:
            zmm1.q[i] = zmm2.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VINSERTF64X2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS

All 686 AVX10.1 instructions