Instruction
VINSERTF64X2
Replaces the 128-bit block that an immediate selects with two doubles from a register or memory.
- Extensions
- Forms
- 4 (4 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VINSERTF64X2 ymm {k}{z}, ymm, xmm, imm8
VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 | EVEX.256.66.0F3A.W1 18 /r ib | AVX10.1 or AVX512DQ + AVX512VL |
VINSERTF64X2 ymm {k}{z}, ymm, m128, imm8
VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 | EVEX.256.66.0F3A.W1 18 /r ib | AVX10.1 or AVX512DQ + AVX512VL |
VINSERTF64X2 zmm {k}{z}, zmm, xmm, imm8
VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 | EVEX.512.66.0F3A.W1 18 /r ib | AVX10.1 or AVX512DQ |
VINSERTF64X2 zmm {k}{z}, zmm, m128, imm8
VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 | EVEX.512.66.0F3A.W1 18 /r ib | AVX10.1 or AVX512DQ |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VINSERTF64X2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm256_mask_broadcast_f64x2
__m256d _mm256_mask_broadcast_f64x2(__m256d __O, __mmask8 __M, __m128d __A) |
|
_mm256_mask_insertf64x2
__m256d _mm256_mask_insertf64x2(__m256d W, __mmask8 U, __m256d A, __m128d B, const int imm) |
|
_mm256_maskz_broadcast_f64x2
__m256d _mm256_maskz_broadcast_f64x2(__mmask8 __M, __m128d __A) |
|
_mm256_maskz_insertf64x2
__m256d _mm256_maskz_insertf64x2(__mmask8 U, __m256d A, __m128d B, const int imm) |
|
_mm512_insertf64x2
__m512d _mm512_insertf64x2(__m512d A, __m128d B, const int imm) |
|
_mm512_mask_insertf64x2
__m512d _mm512_mask_insertf64x2(__m512d W, __mmask8 U, __m512d A, __m128d B, const int imm) |
|
_mm512_maskz_insertf64x2
__m512d _mm512_maskz_insertf64x2(__mmask8 U, __m512d A, __m128d B, const int imm) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512DQ_256 | AVX10.1 or AVX512DQ + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512DQ_512 | AVX10.1 or AVX512DQ | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VGATHERDPS
- VGATHERQPD
- VGATHERQPS
- VGETEXPPD
- VGETEXPPH
- VGETEXPPS
- VGETEXPSD
- VGETEXPSH
- VGETEXPSS
- VGETMANTPD
- VGETMANTPH
- VGETMANTPS
- VGETMANTSD
- VGETMANTSH
- VGETMANTSS
- VGF2P8AFFINEINVQB
- VGF2P8AFFINEQB
- VGF2P8MULB
- VINSERTF32X4
- VINSERTF32X8
- VINSERTF64X4
- VINSERTI32X4
- VINSERTI32X8
- VINSERTI64X2
- VINSERTI64X4
- VINSERTPS
- VMAXPD
- VMAXPH
- VMAXPS
- VMAXSD
- VMAXSH
- VMAXSS
- VMINPD
- VMINPH
- VMINPS
- VMINSD
- VMINSH
- VMINSS
- VMOVAPD
- VMOVAPS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.