VINSERTF64X4

VINSERTF64X4 copies a ZMM source to the destination with its low or high 256 bits, chosen by bit 0 of the immediate, replaced by a YMM register or 32 bytes of memory, and writes the result under a mask of doubles. It is VINSERTI64X4 under a floating-point name, with the same bits moved and the same AVX-512F requirement; that page shows the usual job, joining two halves into one register. Nothing is converted, and no SIMD exception can arise. VINSERTF32X8 does the same under a mask of singles and needs AVX512DQ.

Recorded on Zen 5#

• Memory into the high half. In vinsertf64x4 zmm1{k3}, zmm2, ymmword ptr [mem], 0x27, bit 0 of 27h chose the high half; K3’s low byte EBh took doubles 5 to 7 from memory and 0, 1 and 3 from ZMM2, and ZMM1 kept doubles 2 and 4.
• One register as source and destination. vinsertf64x4 zmm9{k5}, zmm9, ymm14, 0x3 wrote YMM14’s doubles 1 to 3 into doubles 5 to 7 where K5 (E1h) selected them, and double 4 kept its value.

In compiled code#

Clang 23 at -O2 with -march=x86-64-v4 uses VINSERTF64X4 for every unmasked join of two 256-bit halves, whatever the element type: _mm512_insertf64x4, _mm512_insertf32x8, _mm512_inserti64x4 and a __builtin_shufflevector that concatenates two vectors of four doubles all become vinsertf64x4 zmm0, zmm0, ymm1, 1. GCC 14 matches the instruction to the intrinsic, and for the shuffle emits VSHUFF64X2 after two moves that clear the upper halves. Two 32-byte loads from unrelated addresses are a load and an insert with the second address as memory operand in both.

AMD’s Zen 5 latency spreadsheet gives VINSERTF64X4 one cycle and two per cycle on pipes FP1 and FP2, as VINSERTI64X4.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & 1  # the 256-bit block replaced
for i in range(8):
    if k1[i]:
        if i // 4 == x:
            zmm1.q[i] = src3.q[i % 4]
        else:
            zmm1.q[i] = zmm2.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VINSERTF64X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VGATHERQPD
• VGATHERQPS
• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD

All 686 AVX10.1 instructions