VINSERTI128

VINSERTI128 copies a YMM source to the destination and replaces one 128-bit half of the copy, the low one if bit 0 of the immediate is 0, the high one if it is 1, with 16 bytes from an XMM register or memory. The other bits of the immediate are not used. It is the usual way to put two 128-bit values into one YMM register:

• _mm256_set_m128i(hi, lo) becomes vinserti128 ymm0, ymm0, xmm1, 1 in GCC 14 at -O2, and in Clang 23 when integer instructions use the result, with lo already in the low half of YMM0, so the low half needs no instruction of its own.
• Two 16-byte loads from unrelated addresses, such as two rows of an image, become a load and VINSERTI128 with a memory operand.
• _mm256_broadcastsi128_si256 of a register inserts the register into itself; from memory, both compilers use VBROADCASTI128 instead.

Clang also turns _mm256_permute2x128_si256(a, b, 0x20) into VINSERTI128, which reads only 16 bytes when b is in memory, and an insert into the low half into the blend VPBLENDD; GCC emits VINSERTI128 with an immediate of 0 there.

Lanes#

Most AVX and AVX2 instructions work within each 128-bit lane, and Intel’s optimization guide shows how loading the data of two iterations into the two lanes with inserts lets 128-bit algorithms run on YMM registers without lane-crossing shuffles (Sections 15.4.1 and 15.4.2). It also notes that in Crestmont the memory form takes two micro-ops of which the second waits for the first, while the register form runs both halves in parallel (Section 4.1.9.3).

VINSERTF128 does the same and needs only AVX; Clang emits it instead, for integer data too, when no integer instruction uses the result, as in a function that only joins two halves. The EVEX forms are VINSERTI32X4 and its kin, which insert 128 or 256 bits into ZMM registers, under a mask of doublewords or quadwords. VEXTRACTI128 is the reverse.

In the optimization guide

What the optimization guide says about VINSERTI128, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

ymm1.write(ymm2.read())
ymm1.dq[imm8 & 1] = src3.dq[0]
# ymm1 is zeroed from bit 256 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-6

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VINSERTI128, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VBROADCASTI128
• VBROADCASTSD
• VBROADCASTSS
• VEXTRACTI128
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VMOVNTDQA
• VMPSADBW
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ

All 138 AVX2 instructions