VINSERTI32X8

VINSERTI32X8 copies a ZMM source to the destination with its low or high 256 bits, chosen by bit 0 of the immediate, replaced by a YMM register or 32 bytes of memory, and writes the result under a mask of doublewords. It exists only at 512 bits and needs AVX512DQ (or AVX10.1). Unmasked it gives the same result as VINSERTI64X4, which needs only AVX512F and whose page covers joining two halves; the difference is the element size of the mask, as between VINSERTI32X4 and VINSERTI64X2 for 128-bit blocks.

On Zen 5, vinserti32x8 zmm9{k7}, zmm9, ymm14, 0CDh used only bit 0 of 0CDh and put YMM14 in the high half; with F2E3h in the low 16 bits of K7, doublewords 9 and 12 to 15 took values from YMM14 and doublewords 8, 10 and 11 kept their old ones, as did the low half, whose selected doublewords received its own values again.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 both compile the masked _mm512_mask_inserti32x8 to VINSERTI32X8. Unmasked, the element size no longer matters and the compilers part: _mm512_inserti32x8(x, y, 1) is VINSERTI32X8 in GCC and VINSERTF64X4 in Clang, which uses the floating-point name for every unmasked insert of this kind. Without AVX512DQ, as with -mavx512f, the intrinsic does not compile at all, while the 64-bit one does.

AMD’s Zen 5 latency spreadsheet gives VINSERTI32X8 one cycle and two per cycle on pipes FP1 and FP2, the same as VINSERTI64X4. Zen 5’s 2 recorded cases cover the register and memory forms.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & 1  # the 256-bit block replaced
for i in range(16):
    if k1[i]:
        if i // 8 == x:
            zmm1.d[i] = src3.d[i % 8]
        else:
            zmm1.d[i] = zmm2.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VINSERTI32X8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VGETEXPPD
• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32

All 686 AVX10.1 instructions