VINSERTI64X2

VINSERTI64X2 copies a YMM or ZMM source to the destination with one 128-bit block replaced by 16 bytes from an XMM register or memory, then writes the result under a mask of quadwords. It is VINSERTI32X4 with a quadword mask, which that page names as its only difference; the block is chosen the same way, by bits 1:0 of the immediate in a ZMM register and bit 0 in a YMM one, and it needs AVX512DQ where VINSERTI32X4 needs only AVX-512F.

Recorded on Zen 5#

• Immediate bits ignored. vinserti64x2 ymm14, ymm8, xmmword ptr [mem], 0x1a used bit 0 of 1Ah, 0, and put the memory quadwords in the low half, with YMM8’s high half above them and bits 511:256 cleared.
• Quadword mask, zeroing. vinserti64x2 ymm0{k5}{z}, ymm31, xmm16, 0xec put XMM16 in the low half, but with only bit 0 of the four that count set in K5 it wrote quadword 0 alone and zeroed the other three.
• Merging. In vinserti64x2 zmm14{k6}, zmm8, xmm29, 0x3c, K6’s low byte A4h selected quadwords 2, 5 and 7, all from the ZMM8 copy; ZMM14 kept its other five.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile the masked intrinsics _mm512_mask_inserti64x2 and _mm256_maskz_inserti64x2 to VINSERTI64X2. Unmasked, GCC keeps VINSERTI64X2 for _mm512_inserti64x2 and for _mm256_inserti64x2, where the EVEX encoding does what the VEX VINSERTI128 does; Clang emits VINSERTF32X4 and VINSERTF128 there, the same bits under other names.

AMD’s Zen 5 latency spreadsheet gives VINSERTI64X2 one cycle and two per cycle on pipes FP1 and FP2, as VINSERTI32X4.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & (VL // 128 - 1)  # the 128-bit block replaced
for i in range(VL // 64):
    if k1[i]:
        if i // 2 == x:
            zmm1.q[i] = src3.q[i % 2]
        else:
            zmm1.q[i] = zmm2.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VINSERTI64X2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VGETEXPPH
• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64

All 686 AVX10.1 instructions