VINSERTI64X4

VINSERTI64X4 copies a ZMM source to the destination with its low or high 256 bits, chosen by bit 0 of the immediate, replaced by a YMM register or 32 bytes of memory, and writes the result under a mask of quadwords. It exists only at 512 bits and needs only AVX512F. It is the 512-bit counterpart of VINSERTI128, and like it the usual way to put two halves into one register. VINSERTI32X8 does the same with a mask of doublewords and needs AVX512DQ.

On Zen 5, vinserti64x4 zmm5{k7}, zmm5, ymmword ptr [mem], 82h used only bit 0 of 82h and replaced the low half; with E3h in the low byte of K7, quadwords 0 and 1 came from memory and quadwords 2 and 3 kept their old values.

Joining halves#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_inserti64x4(_mm512_castsi256_si512(lo), hi, 1), a zmm register made of two ymm halves, to one insert with lo already in the low half of the destination, so the low half costs nothing. Two 32-byte loads from unrelated addresses become a load and an insert whose memory operand is the second address. GCC emits VINSERTI64X4 for these, and Clang VINSERTF64X4, as it does for all unmasked inserts of integer data at this width; under a mask both use VINSERTI64X4.

Intel’s optimization manual uses such a load-and-insert to compare two lists of indices at once: in its sparse dot product, eight 32-bit indices of one vector go into the low half and eight of the other, loaded by VINSERTI64X4, into the high half, so that one VPCONFLICTD, which compares each element with all elements below it, checks every index of the high half against every index of the low half (Section 17.16.2, Example 17-25). VEXTRACTI64X4 is the reverse.

AMD’s Zen 5 latency spreadsheet gives VINSERTI64X4 one cycle and two per cycle on pipes FP1 and FP2. Zen 5’s 2 recorded cases cover the register and memory forms.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = imm8 & 1  # the 256-bit block replaced
for i in range(8):
    if k1[i]:
        if i // 4 == x:
            zmm1.q[i] = src3.q[i % 4]
        else:
            zmm1.q[i] = zmm2.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E6NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VINSERTI64X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VGETEXPPS
• VGETEXPSD
• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16

All 686 AVX10.1 instructions