VINSERTPS instruction (AVX, AVX10.1)

VINSERTPS is INSERTPS with a separate first source: the elements that the immediate neither replaces nor clears come from that register instead of the destination, and the register is cleared above bit 127. INSERTPS’s page explains the three fields of the immediate and how compilers build vectors with it. There is only a 128-bit form: Intel’s entry raises #UD for VEX.L = 1, and the EVEX form (AVX-512F or AVX10.1) adds no write mask, only XMM16 to XMM31. The VEX form needs AVX, and a memory source of four bytes needs no alignment.

Recorded on Zen 5

vinsertps xmm8, xmm15, xmm0, 69h took element 1 of XMM0 into element 2, cleared elements 0 and 3, and kept element 1 of XMM15.
vinsertps xmm12, xmm6, dword ptr [mem], 5Dh wrote the loaded single to element 1 and cleared the other three, so nothing of XMM6 was left; bits 7:6, 01 here, play no part with a memory source.
{evex} vinsertps xmm24, xmm3, dword ptr [mem], 26h wrote the value to element 2 and then cleared elements 1 and 2, as INSERTPS’s case shows: the clearing comes last.

Wider vectors in compiled code

In our builds at -O2, setting one element of a vector of four floats, v[2] = a, is vinsertps xmm0, xmm0, xmm1, 20h with -march=x86-64-v3 and -v4 in GCC 14 and Clang 23, and Clang builds _mm_setr_ps(a, b, c, 0) with 1Ch and 28h, as for SSE4.1. A vector of eight floats has no such instruction. For v[5] = a, GCC takes the upper 128 bits out with VEXTRACTF128, inserts with 10h and puts them back with VINSERTF128, the 32x4 forms of both at -v4; Clang broadcasts the float with VBROADCASTSS and picks element 5 with vblendps ymm0, ymm0, ymm1, 0x20, two instructions instead of three.

AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike one macro-op with a latency of 1 cycle on any of the four vector pipes, the figures of INSERTPS. VEXTRACTPS goes the other way.

Forms

Every encoding of VINSERTPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VINSERTPS xmm, xmm, m32, imm8` VINSERTPS_XMMdq_XMMdq_MEMd_IMMb	`VEX.128.66.0F3A.WIG 21 /r ib`	AVX
`VINSERTPS xmm, xmm, xmm, imm8` VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb	`VEX.128.66.0F3A.WIG 21 /r ib`	AVX
`VINSERTPS xmm, xmm, xmm, imm8` VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512	`EVEX.128.66.0F3A.W0 21 /r ib`	AVX10.1 or AVX512F
`VINSERTPS xmm, xmm, m32, imm8` VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512	`EVEX.128.66.0F3A.W0 21 /r ib`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, m32, imm8`	`xmm, xmm, xmm, imm8`
Sandy Bridge, Haswell, Skylake, Skylake-SP, Ice Lake	7 / 1p5	1 / 1p5
Broadwell	6 / 1p5	1 / 1p5
Alder Lake, Sapphire Rapids	8 / 1p5	1 / 1p5
Lunar Lake	7 / 2V2 V3	1 / 0.5V2 V3
Piledriver	7 / 1.5FPFMA FPU0 FPU1	2 / 1FPFMA FPU0 FPU1
Zen, Zen 2	8 / 0.5FPU1 FPU2	1 / 0.5FPU1 FPU2
Zen 3, Zen 4	8 / 0.5FP1 FP2	1 / 0.5FP1 FP2
Jaguar	6 / 1FPA FPM FPU0 FPU1	1 / 0.5FPA FPM FPU0 FPU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Insert: imm8[7:6] picks a single of xmm3, imm8[5:4] where it goes in xmm2, and imm8[3:0] which singles are zeroed; the rest of the result comes from xmm2.

With m32, the single is the one in memory, and imm8[7:6] is not used. Example: imm8 = 0x9A.

With imm8 = 0x9A, result singles 3 to 0: 0, a2, 0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if src3.is_memory:
    x = src3.d[0]
else:
    x = src3.d[imm8 >> 6]
for i in range(4):
    if imm8 >> i & 1:
        xmm1.d[i] = 0
    elif i == imm8 >> 4 & 3:
        xmm1.d[i] = x
    else:
        xmm1.d[i] = xmm2.d[i]
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VINSERTPS xmm, xmm, xmm/m32, imm8`
`xmm`	explicit	write
`xmm`	explicit	read
`xmm/m32`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-5
EVEX forms: AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VINSERTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_insert_ps` `__m128 _mm_insert_ps(__m128 X, __m128 Y, const int N)`	`VINSERTPS xmm, xmm, xmm, imm8` VEX.128 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512F_128N

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Recorded on Zen 5#

Wider vectors in compiled code#