Instruction
VLDMXCSR
Loads the MXCSR register, the SSE control and status bits, from memory; the VEX form of LDMXCSR.
- Extensions
- Forms
- 1 (1 VEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VLDMXCSR m32
VLDMXCSR_MEMd | VEX.LZ.NP.0F.WIG AE /2 | AVX |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
v = src.read()
if v & ~mxcsr_mask: # a bit the processor does not have
fault(GP, 0)
mxcsr = v # a flag set with its mask clear
# raises nothing here, nor later:
# an instruction raises only what
# it reports itself
Run on AMD Zen 5 (EPYC 9645): 4 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
VLDMXCSR m32 | ||
m32 | explicit | read |
MXCSR | implicit | write |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
avx-type-5L
Attributes
What else XED records about the forms. How to read.
- All forms
- follows MXCSR
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX | AVX | Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 |
More AVX instructions
- VCVTSS2SI
- VCVTTPD2DQ
- VCVTTPS2DQ
- VCVTTSD2SI
- VCVTTSS2SI
- VDIVPD
- VDIVPS
- VDIVSD
- VDIVSS
- VDPPD
- VDPPS
- VEXTRACTF128
- VEXTRACTPS
- VHADDPD
- VHADDPS
- VHSUBPD
- VHSUBPS
- VINSERTF128
- VINSERTPS
- VLDDQU
- VMASKMOVDQU
- VMASKMOVPD
- VMASKMOVPS
- VMAXPD
- VMAXPS
- VMAXSD
- VMAXSS
- VMINPD
- VMINPS
- VMINSD
- VMINSS
- VMOVAPD
- VMOVAPS
- VMOVD
- VMOVDDUP
- VMOVDQA
- VMOVDQU
- VMOVHLPS
- VMOVHPD
- VMOVHPS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-539 (LDMXCSR)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.