VMASKMOVPD instruction (AVX)

In the optimization guide

What the optimization guide says about VMASKMOVPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

Masks and masked memory access: AVX’s VMASKMOV loads and stores can take assists of hundreds of cycles on Intel’s cores and are slow stores on Zen 3 and Zen 4.

Crestmont and Gracemont

Vectors and AVX2: Masked loads and stores run one every two cycles on 256 bits, slower when a masked-off element would fault.

Skylake to Cooper Lake

Loads, stores and caches: Loads after a vmaskmov store no longer wait for its mask to be known.

Zen 3

Vectors and floating point: LLVM’s model makes a 256-bit VMASKMOVPS store 42 macro-ops that hold the store pipe for 12 cycles, while the masked load is an ordinary load; Zen 3 has none of the AVX-512 stores under a mask register that are ordinary stores on Zen 4.

Zen 4

Vectors and floating point: LLVM’s model makes a 256-bit VMASKMOVPS store 42 macro-ops that hold the store pipe for 12 cycles, while the masked load is an ordinary load, and so is an AVX-512 store under a mask register such as vmovups [rdi]{k1}, ymm0.

Forms

Every encoding of VMASKMOVPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMASKMOVPD xmm, xmm, m128` VMASKMOVPD_XMMdq_XMMdq_MEMdq	`VEX.128.66.0F38.W0 2D /r`	AVX
`VMASKMOVPD ymm, ymm, m256` VMASKMOVPD_YMMqq_YMMqq_MEMqq	`VEX.256.66.0F38.W0 2D /r`	AVX
`VMASKMOVPD m128, xmm, xmm` VMASKMOVPD_MEMdq_XMMdq_XMMdq	`VEX.128.66.0F38.W0 2F /r`	AVX
`VMASKMOVPD m256, ymm, ymm` VMASKMOVPD_MEMqq_YMMqq_YMMqq	`VEX.256.66.0F38.W0 2F /r`	AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A masked load: each double moves where the sign bit of the double in the same place of xmm2 is 1; elsewhere the result is 0.VMASKMOVPD xmm, xmm, m128 VMASKMOVPD ymm, ymm, m256

Example sign bits of xmm2: 10. Every double works alike: 2 and 4 doubles in the xmm and ymm forms.

Result doubles 1 to 0: a1, 0.

A masked store: each double moves where the sign bit of the double in the same place of xmm2 is 1; elsewhere memory is left as it was.VMASKMOVPD m128, xmm, xmm VMASKMOVPD m256, ymm, ymm

Example sign bits of xmm2: 10. Every double works alike: 2 and 4 doubles in the xmm and ymm forms.

Result doubles 1 to 0: a1, unchanged.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VMASKMOVPD xmm, xmm, m128 VMASKMOVPD ymm, ymm, m256

for i in range(VL // 64):
    if ymm2.q[i] >> 63:
        ymm1.q[i] = mem.q[i]
    else:
        ymm1.q[i] = 0
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 2 cases.

VMASKMOVPD m128, xmm, xmm VMASKMOVPD m256, ymm, ymm

for i in range(VL // 64):
    if ymm2.q[i] >> 63:  # the sign bit of the element
        mem.q[i] = ymm3.q[i]
    # else: mem.q[i] is not written

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMASKMOVPD xmm, xmm, m128` `VMASKMOVPD ymm, ymm, m256`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`m128/256`	explicit	read
`VMASKMOVPD m128, xmm, xmm` `VMASKMOVPD m256, ymm, ymm`
`m128/256`	explicit	write
`xmm, ymm`	explicit	read
`xmm, ymm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-6

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMASKMOVPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_maskload_pd` `__m128d _mm_maskload_pd(const double *__p, __m128i __m)`	`VMASKMOVPD xmm, xmm, m128` VEX.128 -mavx
`_mm_maskstore_pd` `void _mm_maskstore_pd(double *__p, __m128i __m, __m128d __a)`	`VMASKMOVPD m128, xmm, xmm` VEX.128 -mavx
`_mm256_maskload_pd` `__m256d _mm256_maskload_pd(const double *__p, __m256i __m)`	`VMASKMOVPD ymm, ymm, m256` VEX.256 -mavx
`_mm256_maskstore_pd` `void _mm256_maskstore_pd(double *__p, __m256i __m, __m256d __a)`	`VMASKMOVPD m256, ymm, ymm` VEX.256 -mavx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions