VMASKMOVPS

VMASKMOVPS moves singles between memory and a vector register only where a mask says so. The mask is a second XMM or YMM register, and only the sign bit of each of its elements counts, so the result of a compare such as VCMPPS can be used as it is. A load writes zero where the mask bit is clear; a store leaves the memory there untouched. There is no form between two registers, which is VBLENDVPS’s job, and, unlike MASKMOVDQU, no non-temporal hint.

Faults on masked-off elements#

Intel’s manuals promise that no fault comes from an element whose mask bit is clear: an all-zero mask cannot fault at all, whatever the address. That makes it tempting for loop tails that would otherwise read past the end of an array. AMD’s manual, Volume 4, does not promise it: the exception and trap behavior of the elements left out is implementation-dependent, and a processor may report a page fault or a data breakpoint for them. Code meant for both should keep the masked-off part of the access on mapped memory. With AVX-512, a masked VMOVUPS with a mask register does the same job; Intel’s optimization manual notes that an all-zero mask there ignores faults without an assist (Table 17-2).

Cost#

Intel’s optimization manual advises VMASKMOV only where a plain VMOVUPS cannot do the job (Section 15.9). A masked load whose masked-off part covers an address that would fault, or with an all-zero mask even a legal address in some addressing forms such as [base+index], can take an assist of hundreds of cycles; since Skylake, so can a store with an all-zero mask to an address that would fault. A load that reads what a masked store wrote waits for the store to reach the cache unless the mask is all ones or all zeros.

In compiled code#

With -mavx2, GCC 14 at -O2 vectorizes if (c[i] > 0) a[i] = b[i] over floats with VCMPLTPS, a VPTEST that skips blocks where no element qualifies, and a VMASKMOVPS load and store; Clang 23 emits the same masked moves without the skip. Intel’s optimization manual also uses the masked store to write a left-packed vector before AVX-512’s compress existed (Section 17.5.1, Example 17-11). VMASKMOVPD is the version for doubles and VPMASKMOVD the AVX2 one for doublewords.

In the optimization guide

What the optimization guide says about VMASKMOVPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Masks and masked memory access: AVX’s VMASKMOV loads and stores can take assists of hundreds of cycles on Intel’s cores and are slow stores on Zen 3 and Zen 4.

Crestmont and Gracemont

• Vectors and AVX2: Masked loads and stores run one every two cycles on 256 bits, slower when a masked-off element would fault.

Jaguar and Puma

• Vectors and floating point: AMD’s spreadsheet gives a VMASKMOVPS load the 6 cycles of a load-op, one per 128 bits, and lists MASKMOVDQU as microcoded; LLVM’s model gives MASKMOVDQU 34 cycles and 63 micro-ops. sources differ

Skylake to Cooper Lake

• Loads, stores and caches: Loads after a vmaskmov store no longer wait for its mask to be known.

Zen 3

• Vectors and floating point: LLVM’s model makes a 256-bit VMASKMOVPS store 42 macro-ops that hold the store pipe for 12 cycles, while the masked load is an ordinary load; Zen 3 has none of the AVX-512 stores under a mask register that are ordinary stores on Zen 4.

Zen 4

• Vectors and floating point: LLVM’s model makes a 256-bit VMASKMOVPS store 42 macro-ops that hold the store pipe for 12 cycles, while the masked load is an ordinary load, and so is an AVX-512 store under a mask register such as vmovups [rdi]{k1}, ymm0.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if ymm2.d[i] >> 31:
        ymm1.d[i] = mem.d[i]
    else:
        ymm1.d[i] = 0
# ymm1 is zeroed from bit VL up

for i in range(VL // 32):
    if ymm2.d[i] >> 31:  # the sign bit of the element
        mem.d[i] = ymm3.d[i]
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-6

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMASKMOVPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VCVTTSD2SI
• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS

All 253 AVX instructions