VMAXBF16

VMAXBF16 keeps the larger bfloat16 value of each pair, 8, 16 or 32 pairs per register, by the rule of VMAXPS: the first source comes back only when it is greater than the second, and the second source otherwise, so two zeros of either sign or a NaN in either source give the second source, a signaling NaN unchanged. It belongs to AVX10.2, with the fixed rules of VADDBF16’s page: denormal inputs read as zeros, no exceptions and no MXCSR. The opcode is 5Fh in EVEX map 5 with the 66 prefix and W0, the byte of VMAXPH, which has no prefix. VMINBF16 is the mirror image, and VMINMAXBF16 offers the IEEE 754-2019 operations.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 vectorizes Z[i] = X[i] > Y[i] ? X[i] : Y[i] over global __bf16 arrays into VMAXBF16 with X first and Y from memory, which is the instruction’s rule, and the ReLU X[i] > 0 ? X[i] : 0 into VMAXBF16 against a zeroed register. Denormals are where the two part: for X = 0001h and Y = 0000h the C expression yields 0001h, while VMAXBF16 reads both as zero and returns Y. fmaxf on __bf16 elements, which must ignore a NaN in either operand, becomes VMAXBF16 with the operands swapped, a VCMPBF16 for unordered and a masked VMOVDQU16 that takes Y where X is a NaN.

With -ffast-math, or with -ffinite-math-only and -fno-signed-zeros together, Clang 23.1.2 stops with “Cannot select” on X86ISD::FMAXC for a bfloat16 vector, at all three widths, both for the ReLU loop and for the intrinsic _mm512_max_pbh; each option alone compiles to VMAXBF16. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.bf16[i]
        b = src3.bf16[i]
        zmm1.bf16[i] = fmax(a, b)
    elif zeroing:
        zmm1.bf16[i] = 0
    # else: zmm1.bf16[i] keeps its value
# a NaN or two zeros: b
# m16bcst: src3.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; denormal inputs read as zero; denormal results flushed to zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMAXBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTTSD2USIS
• VCVTTSS2SIS
• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS

All 96 AVX10.2 instructions