VMAXPD

VMAXPD keeps the larger double of each pair by the rule of VMAXPS, whose page covers the encodings and {sae}: the first source comes back only when it is greater than the second, so a NaN in either element, or two zeros of any sign, give the second source as it is. VMINPD is the mirror image. AMD’s Zen 5 guide lists it like VMAXPS, on the pipes FP2 and FP3 with a latency of 2 cycles.

Quiet NaNs are invalid too#

An addition passes a quiet NaN on without a flag; a maximum does not. Intel’s manual counts a quiet NaN source among the invalid operations of MAXPD, while AMD’s table of its exceptions names only a signaling NaN. Zen 5’s recorded cases follow Intel’s:

• vmaxpd xmm0, xmm13, xmm9 with two quiet NaNs, 7FF8000000000000h first and FFF8000000000000h second, returned the second and set IE.
• With a quiet NaN first and a signaling NaN second, the signaling NaN came back unchanged, not quieted; in the other order the quiet one came back, and IE was set.

So code that runs with IE unmasked, or reads IE afterwards, sees a maximum of quiet NaNs as an invalid operation.

In compiled code#

For b[i] > c[i] ? b[i] : c[i] over doubles, GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 emit one VMAXPD per four elements with b as the first source, which gives c where b is a NaN, just as the C expression does. A ReLU, b[i] > 0.0 ? b[i] : 0.0, is VMAXPD against a register cleared by VXORPD, the zero second, so a NaN input comes out as 0. C’s fmax must return the number when only one argument is a NaN: GCC calls the library function for every element, and Clang follows each VMAXPD with VCMPPD (unordered) and VBLENDVPD, as it does for singles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f64[i]
        b = src3.f64[i]
        zmm1.f64[i] = fmax(a, b)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# a NaN or two zeros: b
# m64bcst: src3.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMAXPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VCVTTSS2SI
• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD

All 253 AVX instructions

More AVX10.1 instructions

• VGETEXPSH
• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64

All 686 AVX10.1 instructions