Instruction
VMAXPH
Returns the larger of each pair of packed half-precision values, or the second operand if either is NaN or both are zero.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMAXPH xmm {k}{z}, xmm, xmm
VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | EVEX.128.NP.MAP5.W0 5F /r | AVX10.1 or AVX512_FP16 + AVX512VL |
VMAXPH xmm {k}{z}, xmm, m128/m16bcst
VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 | EVEX.128.NP.MAP5.W0 5F /r | AVX10.1 or AVX512_FP16 + AVX512VL |
VMAXPH ymm {k}{z}, ymm, ymm
VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 | EVEX.256.NP.MAP5.W0 5F /r | AVX10.1 or AVX512_FP16 + AVX512VL |
VMAXPH ymm {k}{z}, ymm, m256/m16bcst
VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 | EVEX.256.NP.MAP5.W0 5F /r | AVX10.1 or AVX512_FP16 + AVX512VL |
VMAXPH zmm {k}{z}, zmm, zmm, {sae}
VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 | EVEX.512.NP.MAP5.W0 5F /r | AVX10.1 or AVX512_FP16 |
VMAXPH zmm {k}{z}, zmm, m512/m16bcst
VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 | EVEX.512.NP.MAP5.W0 5F /r | AVX10.1 or AVX512_FP16 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VMAXPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_max_ph
__m128h _mm_max_ph(__m128h __A, __m128h __B) |
|
_mm_mask_max_ph
__m128h _mm_mask_max_ph(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B) |
|
_mm_maskz_max_ph
__m128h _mm_maskz_max_ph(__mmask8 __U, __m128h __A, __m128h __B) |
|
_mm256_max_ph
__m256h _mm256_max_ph(__m256h __A, __m256h __B) |
|
_mm256_mask_max_ph
__m256h _mm256_mask_max_ph(__m256h __W, __mmask16 __U, __m256h __A, __m256h __B) |
|
_mm256_maskz_max_ph
__m256h _mm256_maskz_max_ph(__mmask16 __U, __m256h __A, __m256h __B) |
|
_mm512_max_ph
__m512h _mm512_max_ph(__m512h __A, __m512h __B) |
|
_mm512_max_round_ph
__m512h _mm512_max_round_ph(__m512h A, __m512h B, const int R) |
|
_mm512_mask_max_ph
__m512h _mm512_mask_max_ph(__m512h __W, __mmask32 __U, __m512h __A, __m512h __B) |
|
_mm512_mask_max_round_ph
__m512h _mm512_mask_max_round_ph(__m512h W, __mmask32 U, __m512h A, __m512h B, const int R) |
|
_mm512_maskz_max_ph
__m512h _mm512_maskz_max_ph(__mmask32 __U, __m512h __A, __m512h __B) |
|
_mm512_maskz_max_round_ph
__m512h _mm512_maskz_max_round_ph(__mmask32 U, __m512h A, __m512h B, const int R) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_FP16_128 | AVX10.1 or AVX512_FP16 + AVX512VL | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512_FP16_256 | AVX10.1 or AVX512_FP16 + AVX512VL | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512_FP16_512 | AVX10.1 or AVX512_FP16 | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VGETEXPSS
- VGETMANTPD
- VGETMANTPH
- VGETMANTPS
- VGETMANTSD
- VGETMANTSH
- VGETMANTSS
- VGF2P8AFFINEINVQB
- VGF2P8AFFINEQB
- VGF2P8MULB
- VINSERTF32X4
- VINSERTF32X8
- VINSERTF64X2
- VINSERTF64X4
- VINSERTI32X4
- VINSERTI32X8
- VINSERTI64X2
- VINSERTI64X4
- VINSERTPS
- VMAXPD
- VMAXPS
- VMAXSD
- VMAXSH
- VMAXSS
- VMINPD
- VMINPH
- VMINPS
- VMINSD
- VMINSH
- VMINSS
- VMOVAPD
- VMOVAPS
- VMOVD
- VMOVDDUP
- VMOVDQA32
- VMOVDQA64
- VMOVDQU16
- VMOVDQU32
- VMOVDQU64
- VMOVDQU8
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.