VMAXPH

VMAXPH keeps the larger half-precision value of each pair, 32 pairs in zmm registers. It is the mirror image of VMINPH, whose page covers what halves change, and follows the rule of VMAXPS: the first source comes back only when it is greater than the second, and the second source otherwise, so a NaN in either or two zeros of any sign give the second source unchanged. Its opcode is 5Fh in EVEX map 5, that of MAXPS, and like VMINPH it takes {sae} on the 512-bit register form but no rounding mode. VADDPH explains the format and the CPUID bits, and VMAXSH is the scalar form.

A ReLU#

x > 0 ? x : 0 keeps x only when the comparison is true, which is the instruction’s rule with the zero as second source: a NaN becomes 0. At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile a loop of it over a _Float16 array to VMAXPH against a zeroed register, GCC on zmm registers, Clang on ymm registers. On one value Clang emits VMAXSH, while GCC compares with VCMPSH into a mask register and moves the value with a zero-masked VMOVSH, which gives the same results.

Reductions#

The running maximum m = a[i] > m ? a[i] : m stays a chain of VMAXSH in both compilers, since the rule makes the order of the operands matter for NaNs and zeros. With -ffast-math GCC broadcasts the first element with VPBROADCASTW, takes the maximum of 32 halves per VMAXPH, and folds the vector at the end with VEXTRACTI64X4, VEXTRACTI32X4 and three VPSRLDQ shifts; Clang keeps the scalar chain, reading each element from memory. The intrinsic _mm512_reduce_max_ph, which Intel’s optimization manual lists among the conveniences built from existing AVX-512 instructions (Section 18.6.2), compiles in both to VMAXPH steps on halving vectors; Clang does the last step on two halves with VCMPSH and a masked VMOVSH instead.

AMD’s Zen 5 guide does not list AVX512-FP16 among Zen 5’s AVX-512 extensions, and this site’s recorded cases include none of VMAXPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.f16[i]
        b = src3.f16[i]
        zmm1.f16[i] = fmax(a, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# a NaN or two zeros: b
# m16bcst: src3.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMAXPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VGETEXPSS
• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8

All 686 AVX10.1 instructions