VMAXPS

VMAXPS keeps the larger single of each pair, by the same rule as the legacy MAXPS: it returns the first source only when that is greater than the second, and the second source otherwise. So when either element is a NaN, or both are zeros, the result is the second source as it is. Intel’s and AMD’s manuals agree on this; MINPS is the mirror image, and its page explains the rule at more length. Zen 5’s recorded cases show it:

• the maximum of +0 and -0 was -0, and that of -0 and +0 was +0;
• with a quiet NaN first and a signaling NaN second, the signaling NaN came back unchanged, still signaling, and IE was set;
• with a signaling NaN first and 1 second, the result was 1, and IE was set: unlike an addition, VMAXPS can drop a NaN;
• with DAZ set, a denormal second source came back as a zero of its sign.

In compiled code#

The rule is that of b > c ? b : c, which GCC 14 and Clang 23 at -O2 compile to VMAXPS for -march=x86-64-v3 (ymm) and x86-64-v4 (zmm in GCC, ymm in Clang). C’s fmaxf must return the number when only one argument is a NaN: GCC calls the library, while Clang adds a check of one argument with VCMPUNORDPS and takes the other where it is a NaN, with VBLENDVPS for x86-64-v3 and a masked VMOVAPS for x86-64-v4. Under -ffast-math both emit VMAXPS alone.

Encodings#

The VEX forms add a separate destination and 256 bits, the EVEX forms masking, a broadcast single and, between 512-bit registers, {sae}: with every exception unmasked, Zen 5 compared a signaling NaN with 1 under {sae}, returned 1 and took no #XM. Code that needs the maximum of IEEE 754-2019, in which +0 is greater than -0 and a NaN input gives a NaN, can use AVX10.2’s VMINMAXPS. AMD’s Zen 5 guide lists VMAXPS with a latency of 2 cycles at every width.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f32[i]
        b = src3.f32[i]
        zmm1.f32[i] = fmax(a, b)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# a NaN or two zeros: b
# m32bcst: src3.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMAXPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VDIVPD
• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXSD
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS

All 253 AVX instructions

More AVX10.1 instructions

• VGETMANTPD
• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS

All 686 AVX10.1 instructions