VMAXSD

VMAXSD is MAXSD in VEX and EVEX encodings: the larger of the low doubles of its two sources, returning the second source for a NaN in either or for two zeros, with the high double copied from the first source and the bits above 127 cleared. MAXSD’s page covers the rule and C’s idioms for it. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1, which adds a write mask on the low double and {sae}; there is no wider form. VMAXSS is the single version and shows why the operand order decides where memory can go. Zen 5’s recorded cases:

• vmaxsd xmm8, xmm15, qword ptr [mem], under MXCSR 7F80H (round toward zero, DAZ clear), compared the largest denormal with the smallest normal double, returned the normal one and set DE, which a maximum reports for a denormal operand while DAZ is clear.
• vmaxsd xmm1{k3}, xmm2, xmm3, {sae}, with bit 0 of K3 set, under 1E40H, where the invalid exception is unmasked, compared the quiet NaNs 7FF8000000000000H and FFF8000000000000H and returned the second with no #XM and IE still clear, though the maximum treats a quiet NaN as invalid. The high double, 1.0, came from XMM2.

From C#

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 and Clang 23 compile a > b ? a : b over doubles to vmaxsd xmm0, xmm0, xmm1, and the running maximum of a global array to a VMOVSD load and vmaxsd xmm0, xmm1, xmm0, the element first, as on VMAXSS’s page. fmax is a library call in GCC; Clang swaps the operands and repairs a NaN first argument with VCMPUNORDSD, through VBLENDVPD at -v3 and through K1 and a masked VMOVSD at -v4. The EVEX features come from intrinsics: _mm_max_round_sd(a, b, _MM_FROUND_NO_EXC) is vmaxsd xmm0, xmm0, xmm1, {sae} and _mm_mask_max_sd a KMOV and a merging VMAXSD.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows one macro-op of 2 cycles on pipes FP2 and FP3, two per cycle. VMINSD is the minimum.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f64[0]
    b = src3.f64[0]
    xmm1.f64[0] = fmax(a, b)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {sae}: no exception flags
# a NaN or two zeros: b
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMAXSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VDIVPS
• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ

All 253 AVX instructions

More AVX10.1 instructions

• VGETMANTPH
• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD

All 686 AVX10.1 instructions