VMAXSH

VMAXSH is the scalar form of VMAXPH: the larger of the low halves of its two sources, the first returned only when it is greater than the second, with bits 127:16 copied from the first source and the bits above 127 cleared. It shares everything else with VMINSH: EVEX map 5 (opcode 5Fh with F3), a write mask on the low half, {sae} and a two-byte memory operand. VMAXSS is the single-precision form, and VADDPH covers the format.

Clamping a half#

x = x < 0 ? 0 : x; x = x > 1 ? 1 : x; on one _Float16 shows the two compilers apart. In our builds at -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 emits VMAXSH with the zero as first source and then VMINSH with 1 as first source, so a NaN in x is the second source both times and comes out as a NaN, as the C code says. GCC 14 tests the lower bound with VCOMISH and a branch, and the upper one with VCMPSH into a mask register and a masked VMOVSH that puts 1 where x is greater, without VMINSH.

With one operand in memory the order of the operands decides again: x > *p ? x : *p becomes vmaxsh xmm0, xmm0, word ptr [rdi] in Clang, the half from memory being the second source, while GCC loads it first with VMOVW. A minimum converted to float is VMINSH followed by VCVTSH2SS in both.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VMAXSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f16[0]
    b = src3.f16[0]
    xmm1.f16[0] = fmax(a, b)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {sae}: no exception flags
# a NaN or two zeros: b
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMAXSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VGETMANTPS
• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS

All 686 AVX10.1 instructions