VMAXSS

VMAXSS is MAXSS in VEX and EVEX encodings: the larger of the low singles of its two sources, by the asymmetric rule that MINPS explains, with singles 1 to 3 copied from the first source and the bits above 127 cleared. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1, which adds a write mask on the low single and {sae} on xmm registers; VMAXPS shows what {sae} does to a signaling NaN. Zen 5’s recorded cases:

• vmaxss xmm8, xmm15, xmm0, under MXCSR 3FC0H, returned +0 from XMM0 for -0 against +0, the second source as the rule says. The upper singles of XMM15 included the signaling NaN 7F812345H, which arrived unchanged, still signaling, and IE stayed clear: copied elements are not operands.
• vmaxss xmm9{k1}{z}, xmm9, dword ptr [mem], with bit 0 of K1 clear, zeroed the low single, which held +infinity, and kept the three above it from XMM9.

The order of the operands#

Only the last operand can be in memory, and the rule makes the order matter. In our builds with -march=x86-64-v3 or x86-64-v4, GCC 14 and Clang 23 compile a > b ? a : b to vmaxss xmm0, xmm0, xmm1, but the running maximum m = fa[i] > m ? fa[i] : m over a global array loads each element with VMOVSS and computes vmaxss xmm0, xmm1, xmm0: the element must be the first source, as it wins only when greater, so it cannot be read from memory in place.

For fmaxf, which must return the number when one argument is a NaN, GCC calls the library at both levels. Clang swaps the operands of VMAXSS and corrects the case of a NaN first argument with VCMPUNORDSS: through VBLENDVPS for x86-64-v3, and for x86-64-v4 through a mask register and a masked VMOVSS, an EVEX use of the write mask on a scalar.

AMD’s latency spreadsheet for Zen 5 lists it at 2 cycles on pipes FP2 and FP3. VMINSS is the minimum.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f32[0]
    b = src3.f32[0]
    xmm1.f32[0] = fmax(a, b)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {sae}: no exception flags
# a NaN or two zeros: b
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMAXSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VDIVSD
• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMINPD
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA

All 253 AVX instructions

More AVX10.1 instructions

• VGETMANTSD
• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS

All 686 AVX10.1 instructions