Instruction
VMCLEAR
Writes the data of the VMCS at a physical address back to its memory region and sets its launch state to clear.
- Extensions
- Forms
- 1 (1 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMCLEAR m64
VMCLEAR_MEMq | 66 0F C7 /6 | VMX |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
if not in_vmx:
fault(UD)
if vmx_nonroot:
vm_exit(19) # the hypervisor emulates it
if CPL > 0:
fault(GP, 0)
p = src.read() # a physical address
basic = msr[IA32_VMX_BASIC]
w = maxphyaddr # the physical-address width, or
if basic >> 48 & 1: # 32 bits where IA32_VMX_BASIC[48]
w = 32 # says so
if p & 0xFFF or p >> w:
vm_fail(2) # not 4-KByte aligned, or past the
# physical-address width
elif p == vmxon_ptr:
vm_fail(3)
else:
vmcs_clear(p) # the processor's copy of the data
# to the region; launch state clear,
# the VMCS no longer active
if p == current_vmcs:
current_vmcs = NO_VMCS
vm_succeed()Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no VMX, and every one raised an exception.
Operands
| Operand | Kind | Action |
|---|---|---|
VMCLEAR m64 | ||
m64 | explicit | read |
RFLAGS | implicit | write |
Flags
| OF | SF | ZF | AF | PF | CF |
|---|---|---|---|---|---|
| All forms | |||||
| 0 | 0 | M | 0 | 0 | M |
Attributes
What else XED records about the forms. How to read.
- All forms
- privileged: CPL 0 only; may abort a TSX transaction
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
VTX | VMX | Core (Merom, Conroe), Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Bonnell, Saltwell, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill Note: XED's AMD chips, which it derives from its Intel chips, have VMX too; AMD processors implement AMD-V (SVM) instead, so this list leaves them out. |
More VMX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Volume 3C, page 33-11 (VMCLEAR)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.