Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMFUNC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMFUNC VMFUNCNP 0F 01 D4Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not vmx_nonroot:
    fault(UD)                    # outside a guest (and on AMD's
                                 # processors, which have no VMX)
p = current_vmcs
pri = vmcs_read(p, 0x4002)       # processor-based controls; bit
sec = 0                          # 31 activates the secondary ones
if pri >> 31:
    sec = vmcs_read(p, 0x401E)
if not sec >> 13 & 1 or eax > 63:
    fault(UD)                    # VM functions off, or past 63
if not vmcs_read(p, 0x2018) >> eax & 1:
    vm_exit(59)                  # a function the hypervisor did not
                                 # enable
if eax == 0:                     # EPTP switching (28.5.7.3)
    if ecx > 511:
        vm_exit(59)
    a = vmcs_read(p, 0x2024)     # the EPTP list, 512 entries
    e = phys_read(a + 8 * ecx, 64)
    old = vmcs_read(p, 0x201A)   # EPTP
    walk = (e ^ old) >> 3 & 7    # another page-walk length
    if not eptp_ok(e) or walk:
        vm_exit(59)              # or an EPTP that a VM entry would
                                 # refuse
    vmcs_write(p, 0x201A, e)     # the guest's memory, translated by
                                 # other EPT paging structures
    ctls = msr[IA32_VMX_PROCBASED_CTLS2]
    if ctls >> 50 & 1:           # EPT-violation #VE may be 1: the
        vmcs_write(p, 0x0004, ecx)  # EPTP index
# no other VM function is defined; one that is enabled but not
# defined does what the SDM does not say

Run on AMD Zen 5 (EPYC 9645): 2 cases. Every one raised an exception, at CPL 3, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VMFUNC
EAXimplicitread

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
VMFUNC

No CPUID bit: VMX reports VM functions in the IA32_VMX_PROCBASED_CTLS2 MSR, as the allowed setting of the "enable VM functions" control (bit 13).

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Mill

More VMX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Volume 3C, page 33-13 (VMFUNC)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.